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ADSP-SC58x GICDST Register Descriptions
Shared Peripheral Interrupt Processor Targets Register
The
GICDST_SPI_TRGT[n]
GIC.
Figure 7-72: GICDST_SPI_TRGT[n] Register Diagram
Table 7-75: GICDST_SPI_TRGT[n] Register Fields
Bit No.
(Access)
7:0
VALUE
(R/W)
7–106
register provides an 8-bit CPU targets field for each interrupt supported by the
VALUE (R/W)
Shared Peripheral Interrupt Processor
Targets
Bit Name
Shared Peripheral Interrupt Processor Targets.
The GICDST_SPI_TRGT[n].VALUE bit field stores the list of processors that the
interrupt is sent to if it is asserted.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Description/Enumeration
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