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Receive Control Register
The
register enables the SPI receive channel, initiates receive transfers, and configures
SPI_RXCTL
buffer watermark settings.
RRWM (R/W)
Receive FIFO Regular Watermark
RDO (R/W)
Receive Data Overrun
RDR (R/W)
Receive Data Request
RUWM (R/W)
Receive FIFO Urgent Watermark
Figure 16-33: SPI_RXCTL Register Diagram
Table 16-31: SPI_RXCTL Register Fields
Bit No.
(Access)
18:16
RUWM
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Receive FIFO Urgent Watermark.
The SPI_RXCTL.RUWM bits select the receive FIFO (SPI_RFIFO) watermark level
for urgent data bus requests. The SPI also uses this watermark level for generation of
the SPI_ILAT.RUWM interrupt. When an urgent
bled with SPI_RXCTL.RUWM, the SPI_RXCTL.RRWM selection is used as the
deassertion condition for any SPI_ILAT.RUWM interrupts that are latched.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disabled
1 25% full RFIFO
2 50% full RFIFO
3 75% full RFIFO
4 Full RFIFO
5 Reserved
6 Reserved
7 Reserved
ADSP-SC58x SPI Register Descriptions
REN (R/W)
Receive Enable
RTI (R/W)
Receive Transfer Initiate
RWCEN (R/W)
Receive Word Counter Enable
SPI_RFIFO
SPI_RFIFO
watermark is ena-
16–65
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