Analog Devices ADSP-SC58 Series Hardware Reference Manual page 62

Clock Stretching During Repeated Start.............................................................................................. 30–11
TWI Programming Model......................................................................................................................... 30–12
General Setup ......................................................................................................................................... 30–12
Slave Mode ............................................................................................................................................. 30–13
Master Mode Program Flow ................................................................................................................... 30–14
Master Mode Clock Setup ...................................................................................................................... 30–15
Master Mode Transmit ........................................................................................................................... 30–15
Master Mode Receive.............................................................................................................................. 30–16
ADSP-SC58x TWI Register Descriptions ................................................................................................. 30–17
SCL Clock Divider Register ................................................................................................................... 30–18
Control Register .................................................................................................................................... 30–19
FIFO Control Register .......................................................................................................................... 30–21
FIFO Status Register ............................................................................................................................. 30–23
Interrupt Mask Register ......................................................................................................................... 30–24
Interrupt Status Register ........................................................................................................................ 30–26
Master Mode Address Register ............................................................................................................... 30–29
Master Mode Control Registers ............................................................................................................. 30–30
Master Mode Status Register ................................................................................................................. 30–33
Rx Data Double-Byte Register ............................................................................................................... 30–36
Rx Data Single-Byte Register ................................................................................................................. 30–37
Slave Mode Address Register ................................................................................................................. 30–38
Slave Mode Control Register ................................................................................................................. 30–39
Slave Mode Status Register .................................................................................................................... 30–41
Tx Data Double-Byte Register ............................................................................................................... 30–42
Tx Data Single-Byte Register ................................................................................................................. 30–43
Ethernet Media Access Controller (EMAC)
EMAC Features............................................................................................................................................ 31–1
EMAC Functional Description .................................................................................................................... 31–3
ADSP-SC58x EMAC Register List ........................................................................................................... 31–4
lxii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference