Table of Contents
Advertisement
ADSP-SC58x DMC Register Descriptions
PHY Control 1 Register
The
DMC_PHY_CTL1
Figure 10-31: DMC_PHY_CTL1 Register Diagram
Table 10-41: DMC_PHY_CTL1 Register Fields
Bit No.
(Access)
19
BYPODTEN
(R/W)
10–72
register controls programmable PHY features.
15
14
0
0
31
30
0
0
BYPODTEN (R/W)
Bypass ODTEN for DQ and DQS
Bit Name
Bypass ODTEN for DQ and DQS.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Reserved
1 Reserved
5
4
3
2
1
0
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
0
Advertisement
Table of Contents
