Analog Devices ADSP-SC58 Series Hardware Reference Manual page 890

Table 18-43: 16-bit Split Transmit Mode with SPLTEO = 1, SUBSPLTODD = 1, and SWAPEN = 1
DMACFG = 1
DMA0 DATA (32 bits)
Y Y
1 0
Y Y
3 2
Configuring 16-Bit Split Transmit Mode with SPLTWRD=1
For 16-bit split transmit mode, the EPPI_CTL.PACKEN bit is not valid. The EPPI always unpacks the 32-bit
DMA data into two 16-bit words to transmit. The EPPI_CTL.SPLTWRD bit is only valid when the
EPPI_CTL.DLEN bit =16 bits.
Table 18-44: 16-bit Split Transmit Mode with SPLTWRD = 1, SUBSPLTODD = 0, and SWAPEN = 0
DMACFG = 1
DMA0 DATA (32 bits)
Y Y Y Y
3 2 1 0
Y Y Y Y
7 6 5 4
Table 18-45: 16-bit Split Transmit Mode with SPLTWRD = 1, SUBSPLTODD = 1, and SWAPEN = 0
DMACFG = 1
PRIMARY DMA DATA
(32 bits)
Y Y Y Y
3 2 1 0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA1 DATA (32 bits) Pin Data (16 bits)
V V V
1 0
U U Y
1 0
V V U
3 2
U U Y
3 2
V
Y
U
Y
DMA1 DATA (32 bits) Pin Data (16 bits)
U V U V V
1 1 0 0
U V U V U
3 3 2 2
V
U
V
U
V
U
SECONDARY DMA Pin Data (16 bits)
DATA (32 bits)
V V V V V
3 2 1 0
DMACFG = 0
DMA0 DATA (32 bits)
V
1
Y
1 1
U
1
0
0
3
0
2
DMACFG = 0
DMA0 DATA (32 bits)
Y U
0 0
Y Y
0 1 3
Y U
1 2
Y Y
1 3 7
Y
2 4
Y
2 5
Y
3 6
Y
3 7
DMACFG = 0
DMA0 DATA (32 bits)
Y V
0 0
Pin Data (16 bits)
V V
1 0 1
Y Y
0 1
U U
1 0
Y
0
V
0
Y
1
U
Y
2
Pin Data (16 bits)
V U V V
1 1 0 0 0
Y Y Y U
2 1 0
V U V V
3 3 2 2 1
Y Y Y U
6 5 4
V
2
U
V
3
U
Pin Data (16 bits)
V V V V
3 2 1 0 0
EPPI Mode Configuration
1
0
Y
0
Y
0 1
Y
2
Y
1 3
Y
4
Y
2 5
Y
6
Y
3 7
Y
0
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