Analog Devices ADSP-SC58 Series Hardware Reference Manual page 824

Sharc+ processor
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Table 17-13: UART_IMSK_CLR Register Fields (Continued)
Bit No.
(Access)
6
ERFCI
(R/W1C)
5
ETFI
(R/W1C)
4
EDTPTI
(R/W1C)
3
EDSSI
(R/W1C)
2
ELSI
(R/W1C)
1
ETBEI
(R/W1C)
0
ERBFI
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Enable Receive FIFO Count Interrupt Mask Clear.
Enable Transmission Finished Interrupt Mask Clear.
Enable DMA TX Peripheral Triggered Interrupt Mask Clear.
Enable Modem Status Interrupt Mask Clear.
Enable Line Status Interrupt Mask Clear.
Enable Transmit Buffer Empty Interrupt Mask Clear.
Enable Receive Buffer Full Interrupt Mask Clear.
ADSP-SC58x UART Register Descriptions
Description/Enumeration
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
17–37

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