Analog Devices ADSP-SC58 Series Hardware Reference Manual page 575

ADSP-SC58x PORT Register List
The PORT module (PORT) regulates the use of the multiplexable processor pins. Every port pin can operate in
general-purpose I/O (GPIO) mode or as an alternate function. This GPIO operation is the default after processor
reset and is controlled by a set of registers that control GPIO functionality. Every bit in these registers represents a
certain GPIO pin of a specific port. For more information on PORT functionality, see the PORT register descrip-
tions.
Table 14-1: ADSP-SC58x PORT Register List
Name
PORT_DATA
PORT_DATA_CLR
PORT_DATA_SET
PORT_DATA_TGL
PORT_DIR
PORT_DIR_CLR
PORT_DIR_SET
PORT_FER
PORT_FER_CLR
PORT_FER_SET
PORT_INEN
PORT_INEN_CLR
PORT_INEN_SET
PORT_LOCK
PORT_MUX
PORT_POL
PORT_POL_CLR
PORT_POL_SET
ADSP-SC58x PINT Register List
The Pin Interrupt module (PINT) controls the pin-to-interrupt assignment in a byte-wide manner. The pin-inter-
rupt assignment registers do not consist of 32 individual bits. They consist of four control bytes, each functioning as
a multiplexer control. For more information, see the PINT register descriptions.
All PINT registers are 32 bits wide and can be accessed by 32-bit load/store instructions. They also support 16-bit
operation where the upper 16 bits are ignored and the application uses the lower 16 bits only. Consequently, all
PINT registers support 32-bit accesses as well as 16-bit accesses for the lower half words. Applications may use faster
16-bit accesses as long as they do not require functionality of upper register halves.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Port x GPIO Data Register
Port x GPIO Data Clear Register
Port x GPIO Data Set Register
Port x GPIO Output Toggle Register
Port x GPIO Direction Register
Port x GPIO Direction Clear Register
Port x GPIO Direction Set Register
Port x Function Enable Register
Port x Function Enable Clear Register
Port x Function Enable Set Register
Port x GPIO Input Enable Register
Port x GPIO Input Enable Clear Register
Port x GPIO Input Enable Set Register
Port x GPIO Lock Register
Port x Multiplexer Control Register
Port x GPIO Polarity Invert Register
Port x GPIO Polarity Invert Clear Register
Port x GPIO Polarity Invert Set Register
PORT Functional Description
14–3