Analog Devices ADSP-SC58 Series Hardware Reference Manual page 150

Functional Description
A5 Configurations
Table 2-2: A5 Core Configuration
Core Feature
JAZELLE Support
NEON Engine
FPU
Instruction cache size
Data cache size
A5 Configuration Signals
Table 2-3: A5 Configuration Signals
Configuration
Default Exception Handler Endianness
CPU ID field
Disable Write access to some CP15 registers
Default exception handling state
Exception vectors' location at reset
Disable invalidate entire data cache, instruc-
tion cache and TLB at reset
Enable the RAM interface clamps
A5 Power Modes
Table 2-4: ARM Core Power Modes
Mode
Run mode
Standby mode
Dormant mode
Shutdown mode
L2CC Configuration Signals
Table 2-5: L2CC Configuration Signals
Configuration
Associativity
2–8
Comment
Implemented
Implemented
Implemented
32 KB
32 KB
A5 TRM Signal Name
CFGEND
CLUSTERID[3:0]
CP15SDISABLE
TEINIT
VINITHI
L1RSTDISABLE
CPURAMCLAMP
Comment
Supported
Supported
Not Supported
Not Supported
L2CC TRM Signal Name
ASSOCIATIVITY
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Comment
Little Endian
4'b0000
Not Enabled
ARM Mode
start exception vectors at address 0x00000000
Disabled
clamps not active
Comment
8-Way