Analog Devices ADSP-SC58 Series Hardware Reference Manual page 765

Table 16-26: SPI_MMRDH Register Fields (Continued)
Bit No.
(Access)
25:24 TRIDMY
(R/W)
23:16 MODE
(R/W)
14:12 DMYSIZE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Tristate Dummy Timing.
The SPI_MMRDH.TRIDMY bits specify whether and when output pins are three-
stated during the interval of time specified by the SPI_MMRDH.DMYSIZE bits. Out-
put pins potentially three-stated include all pins which were used to transmit the ad-
dress
Mode Field.
These bits specify up to a leading byte to be transmitted during the interval of time
specified by the SPI_MMRDH.DMYSIZE bit field. This first byte, or a portion of it,
is interpreted as mode bits when certain opcodes are used in conjunction with certain
SPI memory devices. Mode bits are sent using the same number of pins which were
used to transmit the address. Once sent, output pins will be held in their final resultant
state until the conclusion of all dummy byte periods, unless three-stating the outputs is
specified first by the SPI_MMRDH.TRIDMY bits.
Bytes of Dummy/Mode.
The SPI_MMRDH.DMYSIZE bit field specifies the number of bytes separating ad-
dress transmission and read data return. Dummy bytes elapse assuming dummy bits
are transmitted using the same number of pins which were used to transmit address.
ADSP-SC58x SPI Register Descriptions
Description/Enumeration
0 Tristate outputs immediately
1 Tristate outputs after 4 bits of dummy/mode are trans-
mitted
2 Tristate outputs after 8 bits of dummy/mode are trans-
mitted
3 Never tristate outputs (previously specified output state
is held)
0 0 Bytes
1 1 Bytes
2 2 Bytes
3 3 Bytes
4 4 Bytes
5 5 Bytes
6 6 Bytes
7 7 Bytes
16–59