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Programming Examples
priority level, thus providing the flexibility to have lower-priority interrupt sources considered before higher-
priority sources.
ADDITIONAL INFORMATION: The
programmed to mask the interrupts based on the customized levels and grouping.
Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling
Interrupt handling within an individual core requires specific handshaking with the SEC to ensure that nested inter-
rupts are properly tracked and that new peripheral interrupts being raised within the SEC are either passed immedi-
ately to the core or held off and queued within the SEC for later servicing. Inside the SEC ISR, the following steps
are required:
Use this procedure to write a custom dispatcher inside the Interrupt Service Routine. Note that the core needs to
read the
SEC_CSID[n]
SEC_END
register after the ISR execution completes.
1. Read the
SEC_CSID[n]
2. Write the read value back to the
core has accepted and begun processing for the interrupt request.
3. Execute the actual ISR (typically a call to a specific handler function from a look-up table based on the periph-
eral source ID). Write to the
4. Write the
SEC_CSID[n]
the SEC that the interrupt has now been serviced.
5. Return from interrupt.
With this implementation in place, a higher-priority interrupt being raised by the SEC can be serviced by the core
after step 2. The SEC knows what it passed to the core by virtue of its write to the
the core acknowledges that write, the SEC knows whether or not newly raised peripheral interrupts are higher prior-
ity than the highest-priority interrupt being processed by the core. If the new interrupt is higher priority, it pushes
the current
SEC_CSID[n]
interrupt request. If it is lower priority, the SEC queues the interrupt until the core writes to the
with the source ID of the higher-priority interrupt, thus confirming that it was fully processed, at which point that
value is popped from the internal stack and any pending peripheral interrupt requests are arbitra-
SEC_CSID[n]
ted among before the SEC writes the new
the core self-nests the latched SEC interrupt requests, as needed, when a higher-priority interrupt is presented to it,
and the write to the
SEC_END
required handshaking to signal to the SEC block that each individual source ID interrupt request is fully serviced.
Please refer to the SHARC+ Core Programming Reference for more details regarding SEC handler code.
Configuring a System Source as a Fault
1. Write to the
SEC_GCTL
7–20
SEC_CPMSK[n]
register and acknowledge it by writing the same value. It should also write to the
register to obtain the source ID of the peripheral interrupt request.
SEC_CSID[n]
register to enable the SEC.
SEC_GCTL
of the active interrupt (read in step 1 above) to the
to an internal stack, writes the new
SEC_CSID[n]
register in the SEC handler epilog code guarantees that each nested level has the
register to enable the SEC.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
and
SEC_CGMSK[n]
register to send the acknowledge signal to the SEC that the
SEC_CSID[n]
value and asserts a new interrupt request. Meanwhile,
registers must also can be
SEC_END
register to signal to
register. After
SEC_CSID[n]
value, and asserts a new SEC
SEC_END
register
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