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Global Control Register
The TRU global control register (TRU_GCTL) provides register locking, TRU reset, and TRU enable.
MTRL (R/W)
MTR Lock Bit
RESET (R/W)
Soft Reset
LOCK (R/W)
GCTL Lock Bit
Figure 8-3: TRU_GCTL Register Diagram
Table 8-7: TRU_GCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
2
MTRL
(R/W)
1
RESET
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
GCTL Lock Bit.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the TRU_GCTL.LOCK
bit is enabled, the
MTR Lock Bit.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the TRU_GCTL.MTRL
bit is enabled, the
Soft Reset.
The TRU_GCTL.RESET bit is write-1-action and triggers a soft reset to all TRU reg-
isters.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
register is read only.
TRU_GCTL
0 Read write
1 Read only
register is read only.
TRU_MTR
0 Read write
1 Read only
0 No action
1 Soft reset
ADSP-SC58x TRU Register Descriptions
1
0
0
0
EN (R/W)
Non-MMR Enable
17
16
0
0
8–17
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