Analog Devices ADSP-SC58 Series Hardware Reference Manual page 926

Table 19-2: ADSP-SC58x PWM Interrupt List (Continued)
Interrupt Name
ID
35 PWM2_TRIP
ADSP-SC58x PWM Trigger List
Table 19-3: ADSP-SC58x PWM Trigger List Masters
Trigger ID Name
21 PWM0_SYNC
22 PWM1_SYNC
23
PWM2_SYNC
Table 19-4: ADSP-SC58x PWM Trigger List Slaves
Trigger ID Name
8 PWM0_TRIP_TRIG0
9
PWM0_TRIP_TRIG1
10 PWM0_TRIP_TRIG2
11 PWM1_TRIP_TRIG0
12 PWM1_TRIP_TRIG1
13
PWM1_TRIP_TRIG2
14 PWM2_TRIP_TRIG0
15 PWM2_TRIP_TRIG1
16
PWM2_TRIP_TRIG2
PWM Definitions
The following definitions are helpful when using the PWM module.
Chopping
Used to simplify the design of isolated gate drive circuits for PWM inverters. If using a transformer coupled power
device gate drive amplifier, then the active PWM signal must be chopped at a high frequency.
Dead-Time
A short delay introduced between turning off one PWM signal (for example, AH) and turning on the complementa-
ry signal (for example, AL). This short time delay permits turning off a power switch (AH in this case) to completely
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
PWM2 Trip
Description
PWM0 PWMTMR Grouped
PWM1 PWMTMR Grouped
PWM2 PWMTMR Grouped
Description
PWM0 Trip Trigger Slave 0
PWM0 Trip Trigger Slave 1
PWM0 Trip Trigger Slave 2
PWM1 Trip Trigger Slave 0
PWM1 Trip Trigger Slave 1
PWM1 Trip Trigger Slave 2
PWM2 Trip Trigger Slave 0
PWM2 Trip Trigger Slave 1
PWM2 Trip Trigger Slave 2
Functional Description
Sensitivity DMA
Channel
Level
Sensitivity
Edge
Edge
Edge
Sensitivity
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
19–5