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Fault System Reset Delay Current Register
The SEC fault system reset delay current register (SEC_FSRDLY_CUR) contains the active count
(SEC_FSRDLY_CUR.COUNT field) in (SEC) clock periods for the delay from fault active to system reset assertion,
if enabled. The count is loaded from the
bit is set). The SEC decrements the value in
SEC_FSTAT.ACT bit is set.
Figure 7-23: SEC_FSRDLY_CUR Register Diagram
Table 7-22: SEC_FSRDLY_CUR Register Fields
Bit No.
(Access)
31:0
COUNT
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC_FSRDLY
SEC_FSRDLY_CUR
15
14
0
COUNT[15:0] (R)
Fault System Reset Delay
31
30
0
COUNT[31:16] (R)
Fault System Reset Delay
Bit Name
Fault System Reset Delay.
The SEC_FSRDLY_CUR.COUNT bit field is the active count in (SEC) clock periods
for the delay from fault active to system reset assertion.
register when a fault becomes active (SEC_FSTAT.ACT
each (SEC) clock cycle while the
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x SEC Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
0
7–47
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