Table of Contents
Advertisement
The Fixed Priority table shows the priority for fixed priority mode (with urgent priority disabled) for each SCB
channel.
If two cores (or the 64-bit Max BW DMA) simultaneously try to access L2 for the same instance (both read or both
write), even to different banks, software allows only one master access at a time. One access port can support one
read and write at the same time. However, if one core issues a write and the other issues a read, then access can
proceed simultaneously. There is no extra latency inside L2, as long as the accesses are to different banks (assuming
pending DMA traffic is also to a non-conflicting bank).
When a core and DMA both access the same bank via the same port (both read or both writes), the best access rate
that DMA can achieve is one 64-bit access in every three SYSCLK_0 cycles during the conflict period. This access
rate is achieved by programming the read priority count register (L2CTL_RPCR.RPC0) bit and the write priority
count register (L2CTL_WPCR.WPC0) bit to 0, while programming the L2CTL_RPCR.RPC1 and the
L2CTL_WPCR.WPC1 bits to 1.
Table 9-3: Fixed Priority
Channel
L2 Refresh Request
Port 0 Read Channel
Port 0 Write Channel
Port 1 Read Channel
Port 1 Write Channel
The arbiters also support priority elevation for a particular channel that has been starved of grants for many
SYSCLK_0 cycles. If a channel does not get a grant for N cycles after its request, then that channel can elevate the
priority of its request by issuing an urgent priority request. This request causes that particular channel to become the
highest priority master for the next grant cycle (pipelined arbitration for urgent priority). The number of cycles N,
after which the priority is elevated, can be programmed for each channel separately using the
L2CTL_WPCR
registers.
Programming the bits in the
for DMA. This grant rate of one in three SYSCLK_0 cycles during the conflict period is achievable under the fol-
lowing conflict conditions:
• An access conflict between the core and DMA to the same memory bank in the fixed priority arbitration
scheme with core activity always prioritized over DMA activity
• An access conflict within the pipelined implementation of urgent priority
To disable urgent priority requests, set the L2CTL_CTL.DISURP bit. This bit disables the urgent priority requests
for all port channels. Each channel can also be prevented from raising the urgent priority request through the priori-
ty count register for the specific channel. However, there is no support for disabling urgent priority for a specific
memory bank arbiter.
The Fixed Priority With Priority Elevation table provides the various priority levels for the L2 system memory.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
and
L2CTL_RPCR
L2CTL_WPCR
L2 System Memory Architectural Concepts
Priority Level
5 (highest)
4
3
2
1 (lowest)
registers appropriately achieves the best grant rate
L2CTL_RPCR
and
9–5
Advertisement
Table of Contents
