Analog Devices ADSP-SC58 Series Hardware Reference Manual page 468

ADSP-SC58x DMC Register Descriptions
Table 10-33: DMC_STAT Register Fields (Continued)
Bit No.
(Access)
19:16 PENDREF
(R/NW)
13 DLLCALDONE
(R/NW)
7 RESETDONE
(R/NW)
5 DPDACK
(R/NW)
4 PDACK
(R/NW)
3 SRACK
(R/NW)
10–62
Bit Name
Pending Refresh.
The DMC_STAT.PENDREF bits indicate the number of pending auto-refresh com-
mands whose value can be from "0000" to "0111". When the DMC is in low power
DDR mode (DMC_CTL.LPDDR =1), the maximum value for
DMC_STAT.PENDREF is 3.
DLL Calibration Done.
The DMC_STAT.DLLCALDONE indicates that the PHY DLL calibration sequence is
complete.
Reset Done.
The DMC_STAT.RESETDONE bit indicates that the reset sequence is complete.
Deep Power-Down Acknowledge.
The DMC_STAT.DPDACK bit indicates that deep power-down mode is active. Note
that this status is available in low power DDR mode (DMC_CTL.LPDDR =1) only.
Power-Down Acknowledge.
The DMC_STAT.PDACK bit indicates that power-down mode is active.
Self-Refresh Acknowledge.
The DMC_STAT.SRACK bit indicates that self-refresh mode is active.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
2 2 Clock Cycles Latency
3 3 Clock Cycles Latency
4 4 Clock Cycles Latency
5 5 Clock Cycles Latency
6 6 Clock Cycles Latency
7 7Clock Cycles Latency
0 No Status
1 Completed PHY DLL Calibration
0 SDRAM Reset is ongoing
1 SDRAM Reset is done
0 Not in Deep Power-Down Mode
1 Deep Power-Down Mode Active
0 Not in Power-Down Mode
1 Power-Down Mode Active
0 Not in Self-Refresh Mode
1 Self-Refresh Mode Active