Analog Devices ADSP-SC58 Series Hardware Reference Manual page 617

Port x Function Enable Set Register
The
PORT_FER_SET
ing 1 to a bit in PORT_FER_SET
PX15 (R/W1S)
Port x Bit 15 Mode Set
PX14 (R/W1S)
Port x Bit 14 Mode Set
PX13 (R/W1S)
Port x Bit 13 Mode Set
PX12 (R/W1S)
Port x Bit 12 Mode Set
PX11 (R/W1S)
Port x Bit 11 Mode Set
PX10 (R/W1S)
Port x Bit 10 Mode Set
PX9 (R/W1S)
Port x Bit 9 Mode Set
PX8 (R/W1S)
Port x Bit 8 Mode Set
Figure 14-16: PORT_FER_SET Register Diagram
Table 14-17: PORT_FER_SET Register Fields
Bit No.
(Access)
15 PX15
(R/W1S)
14 PX14
(R/W1S)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register permits enabling peripheral mode for each bit and corresponding GPIO pin. Writ-
enables peripheral mode for the corresponding pin.
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
Port x Bit 15 Mode Set.
The PORT_FER_SET.PX15 bit enables peripheral mode.
Port x Bit 14 Mode Set.
The PORT_FER_SET.PX14 bit enables peripheral mode.
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 No Effect
1 Set Bit for Peripheral Mode
0 No Effect
1 Set Bit for Peripheral Mode
ADSP-SC58x PORT Register Descriptions
2 1 0
0 0 0
PX0 (R/W1S)
Port x Bit 0 Mode Set
PX1 (R/W1S)
Port x Bit 1 Mode Set
PX2 (R/W1S)
Port x Bit 2 Mode Set
PX3 (R/W1S)
Port x Bit 3 Mode Set
PX4 (R/W1S)
Port x Bit 4 Mode Set
PX5 (R/W1S)
Port x Bit 5 Mode Set
PX6 (R/W1S)
Port x Bit 6 Mode Set
PX7 (R/W1S)
Port x Bit 7 Mode Set
18 17 16
0 0 0
14–45