Analog Devices ADSP-SC58 Series Hardware Reference Manual page 712

SPI Functional Description
Figure 16-1: SPI Controller Block Diagram, Quad Mode
Transfer Protocol
The SPI module implements two channels that are independent of each other. The SPI module uses the
SPI_RXCTL and SPI_TXCTL
modes, SPI can enable and use both channels simultaneously.
The SPI protocol supports four different combinations of serial clock phase and polarity. These combinations are
selected through the SPI_CTL.CPOL and SPI_CTL.CPHA bits.
The SPI Transfer Protocol figures demonstrate the two basic transfer formats as defined by the CPHA bit. Two
waveforms are shown for SPI_CLK; one for SPI_CTL.CPOL=0 and the other for SPI_CTL.CPOL=1. The dia-
grams can be interpreted as master or slave timing diagrams since the SPI_CLK, SPI_MISO, and SPI_MOSI
pins are directly connected between the master and the slave. The SPI_MISO signal is the output from the slave
(slave transmission), and the SPI_MOSI signal is the output from the master (master transmission). The master
generates the SPI_CLK signal. The SPI_SS signal is the slave device select input to the slave from the master. The
diagrams represent an 8-bit transfer (SPI_CTL.SIZE=0) with the MSB first (SPI_CTL.LSBF=0). Any combi-
nation of the SPI_CTL.SIZE and SPI_CTL.LSBF bits is permissible. For example, a 16-bit transfer with the
LSB first is another possible configuration.
16–6
SPI_CLK
SPI_RDY
CLK
GEN
CONTROL AND
STATUS REGISTERS
DMA BUS
PERIPHERAL BUS
dedicated control registers to control these channels. Except in dual and quad
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
RSR TSR
RFIFO TFIFO