Analog Devices SHARC ADSP-214 Series Manuals

Analog Devices SHARC ADSP-214 Series Manuals

Manuals and User Guides for Analog Devices SHARC ADSP-214 Series. We have 1 Analog Devices SHARC ADSP-214 Series manual available for free PDF download: Hardware Reference Manual

Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Analog Devices SHARC ADSP-214 Series Hardware Reference Manual (1192 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 8 MB

Table of Contents

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3
- Table of Contents
  3
External Port Dma

12
- Intended Audience
  61
- Preface
  61
- Purpose of this Manual
  61
- Manual Contents
  62
- What's New in this Manual
  65
- Registration for Myanalog.com
  66
- Technical or Customer Support
  66
- Engineerzone
  67
- Social Networking Web Sites
  67
- Supported Processors
  67
- Analog Devices Web Site
  68
- Product Information
  68
- Visualdsp++ Online Documentation
  68
- Technical Library CD
  69
- Notation Conventions
  70
- Design Advantages
  73
- Introduction
  73
- Processor Architectural Overview
  74
- Processor Core
  74
- SHARC Family Product Offerings
  74
- Digital Audio Interface (DAI)
  75
- I/O Peripherals
  75
- I/O Processor
  75
- Digital Peripheral Interface (DPI)
  76
- Interrupt Controller
  76
- Signal Routing Unit
  76
- Development Tools
  77
- Differences from Previous Processors
  77
- Signal Routing Unit 2
  77
- I/O Architecture Enhancements
  78
- Features
  80
- DMA Channel Allocation
  81
- DMA Channel Registers
  81
- Register Overview
  81
- Standard DMA Parameter Registers
  82
- Extended DMA Parameter Registers
  86
- Data Buffers
  88
- Chain Pointer Registers
  89
- TCB Storage
  91
- Serial Port TCB
  92
- Spi Tcb
  92
- Link Port TCB
  93
- Uart Tcb
  93
- FIR Accelerator TCB
  94
- IIR Accelerator TCB
  95
- FFT Accelerator TCB
  96
- External Port TCB
  97
- Automated Data Transfer
  100
- Clocking
  100
- Functional Description
  100
- DMA Transfer Types
  101
- DMA Direction
  102
- Internal to External Memory
  102
- Peripheral to Internal Memory
  102
- DMA Controller Addressing
  103
- Internal Memory to Internal Memory
  103
- Peripheral to External Memory (Sports)
  103
- Internal Index Register Addressing
  105
- DMA Channel Status
  106
- External Index Register Addressing
  106
- DMA Start and Stop Conditions
  107
- Operating Modes
  108
- DMA Chaining
  110
- TCB Memory Storage
  110
- Chain Assignment
  111
- Starting Chain Loading
  112
- TCB Chain Loading Priority
  113
- Chain Insert Mode (Sports Only)
  114
- Fixed DMA Channel Arbitration
  114
- Peripheral DMA Bus
  120
- External Port DMA Bus
  121
- Sport/External Port DMA Bus
  121
- Rotating DMA Channel Arbitration
  122
- Rotating Priority by Group
  122
- Interrupts
  123
- Sources
  123
- Unchained DMA Interrupts
  123
- Chained DMA Interrupts
  124
- Transfer Completion Types
  124
- Access Completion
  125
- Core Single Word Transfer Interrupts
  125
- Internal Transfer Completion
  125
- Interrupt Versus Channel Priorities
  126
- Debug Features
  127
- Effect Latency
  127
- Emulation Considerations
  127
- IOP Effect Latency
  127
- Write Effect Latency
  127
- IOP Throughput
  128
- Programming Model
  128
- General Procedure for Configuring DMA
  129
- External Port
  131
- Features
  132
- Pin Descriptions
  133
- Pin Multiplexing
  133
- Register Overview
  133
- Clocking AMI/SDRAM
  135
- Clocking AMI/DDR2
  136
- External Port Arbitration
  137
- Functional Description
  137
- Arbitration Freezing
  140
- Asynchronous Memory Interface
  140
- Operating Mode
  140
- Features
  141
- Functional Description
  141
- Asynchronous Reads
  142
- Asynchronous Writes
  142
- Address Mapping
  144
- Idle Cycles
  144
- Parameter Timing
  144
- Data Packing
  145
- External Access Extension
  145
- Operating Modes
  145
- Predictive Reads
  146
- Features
  147
- SDRAM Controller (ADSP-2147X/Adsp-2148X)
  147
- Functional Description
  148
- Load Mode Register
  150
- SDRAM Commands
  150
- Bank Activation
  151
- Single Precharge
  151
- Precharge All
  152
- Read/Write
  152
- Auto-Refresh
  154
- Command Truth Table
  154
- No Operation/Command Inhibit
  154
- Address Mapping
  155
- Address Translation Options
  156
- Address Width Settings
  157
- 16-Bit Address Mapping
  158
- Refresh Rate Control
  162
- Internal SDRAM Bank Access
  164
- Single Bank Access
  164
- Multibank Access
  165
- Multi Bank Operation with Data Packing
  166
- Fixed Timing Parameters
  167
- Timing Parameters
  167
- Data Mask
  168
- Operating Modes
  168
- Parallel Connection of Sdrams
  168
- Resetting the Controller
  168
- Buffering Controller for Multiple Sdrams
  169
- SDRAM Read Optimization
  170
- Core Accesses
  171
- DMA Access
  173
- Notes on Read Optimization
  173
- Self-Refresh Mode
  174
- Force Precharge All
  175
- Forcing SDRAM Commands
  175
- DDR2 DRAM Controller (ADSP-2146X)
  176
- Features
  176
- Force Auto-Refresh
  176
- Force Load Mode Register
  176
- Functional Description
  178
- Pin Descriptions
  178
- DDR2 Commands
  181
- Load Mode Register
  181
- Load Extended Mode Register
  182
- Load Extended Mode Register 2
  183
- Conditional Instructions
  216
- Sdram
  216
- SIMD Access
  216
- Ddr2
  217
- External Instruction Fetch
  218
- Interrupt Vector Table (IVT)
  218
- Fetching ISA Instructions from External Memory
  219
- 16-Bit Instruction Storage and Packing
  220
- Instruction Packing
  220
- 8-Bit Instruction Storage and Packing
  222
- Addressing for Various Memory Sizes
  223
- Mixing Instructions and Data in External Bank 0
  223
- Writing Instructions to External Memory
  224
- Instruction Cache
  225
- Fetching VISA Instructions from External Memory
  228
- External Port DMA
  230
- External Port DMA Parameter Registers
  230
- Internal DMA Addressing
  232
- Operating Modes
  232
- Circular Buffered DMA
  233
- Standard DMA
  233
- External Address Calculation
  236
- Scatter/Gather DMA
  236
- Delay Line DMA
  241
- External Address Calculation for Reads
  242
- Interrupts
  244
- Access Completion
  245
- Internal Transfer Completion
  245
- Interrupt Dependency on DMA Mode
  245
- External Port Throughput
  246
- AMI Data Throughput
  247
- SDRAM Throughput
  247
- Throughput Conditional Instructions
  247
- Core Throughput
  248
- DDR2 Throughput
  248
- DMA Throughput
  248
- External Instruction Fetch Throughput
  249
- Dma
  251
- External Port
  251
- Programming Models
  251
- Standard DMA
  251
- Write Effect Latency
  251
- Chained DMA
  252
- Delay Line DMA
  253
- Additional Information
  254
- Disabling and Re-Enabling DMA
  254
- AMI Initialization
  255
- Power-Up Sequence
  256
- SDRAM Controller
  256
- Output Clock Generator Programming Model
  257
- Self-Refresh Mode
  257
- Changing the VCO Clock During Runtime
  258
- DDR2 Controller
  259
- Power-Up Sequence
  259
- Frequency Change in Precharge Power-Down Mode
  260
- External Instruction Fetch
  261
- AMI Configuration
  262
- External Memory Access Restrictions
  262
- SDRAM Configuration
  262
- Link Ports-Adsp-2146X
  265
- Features
  266
- Pin Descriptions
  267
- Register Overview
  267
- Clocking
  268
- Functional Description
  268
- Architecture
  269
- Protocol
  269
- Intercommunication
  271
- Multi-Master Conflicts
  274
- Self-Synchronization
  274
- Example Token Passing
  275
- Data Transfer
  277
- Link Buffers
  277
- Receive Buffer
  278
- Transmit Buffer
  278
- Buffer Status
  279
- Core Transfers
  279
- DMA Transfers
  280
- Interrupts
  280
- Interrupt Service
  281
- Interrupt Sources
  281
- Access Completion
  282
- Internal Transfer Completion
  282
- Chained DMA
  283
- Core Access
  283
- DMA Access
  283
- Service Request Interrupts
  284
- Debug Features
  285
- Shadow Register
  285
- Buffer Hang Disable (BHD)
  286
- Effect Latency
  286
- Link Port Effect Latency
  286
- Programming Model
  286
- Write Effect Latency
  286
- Changing the Link Port Clock
  287
- Receive DMA
  288
- Transmit DMA
  288
- Memory-To-Memory Port Dma
  291
- Clocking
  292
- Features
  292
- Register Overview
  292
- Data Buffer
  293
- Data Transfer Types
  293
- Functional Description
  293
- DMA Transfer
  294
- Interrupts
  294
- Effect Latency
  295
- MTM Effect Latency
  295
- MTM Throughput
  295
- Programming Model
  295
- Write Effect Latency
  295
- Fft/Fir/Iir Hardware Modules
  297
- FFT Accelerator
  299
- Features
  300
- Register Descriptions
  300
- Clocking
  301
- Compute Block
  301
- Functional Description
  301
- Accelerator States
  302
- Coefficient Memory
  302
- Data Memory
  302
- Reset State
  302
- Idle State
  303
- Processing State
  303
- Write State
  303
- Internal Memory Storage
  304
- Large FFT Computation (>= 512 Points)
  307
- Operating Modes
  307
- Small FFT Computation (<= 256 Points)
  307
- Example for FFT Size N=512
  308
- Special Product-Number of Iterations Is N/128 = 4
  308
- Vertical FFT
  308
- Horizontal FFT
  309
- No Repeat Mode
  310
- Repeat Mode
  310
- Unpacked Data Mode
  310
- Inverse FFT
  311
- Configure the FFT Control Register
  320
- N >= 512, no Repeat
  320
- Special Buffer Configuration
  321
- Vertical FFT Configuration
  321
- Horizontal FFT Configuration
  322
- N >= 512, Repeat
  322
- Debug Mode
  323
- Write to Local Memory
  323
- Features
  324
- FIR Accelerator
  324
- Read from Local Memory
  324
- Clocking
  325
- Register Overview
  325
- Functional Description
  326
- Compute Block
  327
- Partial Sum Register
  328
- Coefficient Memory
  329
- Delay Line Memory
  329
- Prefetch Data Buffer
  329
- Processing Output
  330
- Coefficients and Input Buffer Storage
  331
- Internal Memory Storage
  331
- Operating Modes
  333
- Single Rate Processing
  333
- Single Channel Processing
  344
- Multichannel Processing
  345
- Debug Mode
  348
- Read from Local Memory
  348
- Write to Local Memory
  348
- FIR Programming Example
  349
- Single Step Mode
  349
- Features
  351
- IIR Accelerator
  351
- Register Overview
  351
- Clocking
  352
- Functional Description
  352
- Multiply and Accumulate (MAC) Unit
  355
- Coefficient Memory
  356
- Coefficient Memory Storage
  356
- Data Memory
  356
- Internal Memory Storage
  356
- 40-Bit Floating-Point Mode
  357
- Operating Modes
  357
- Window Processing
  357
- Chain Pointer DMA
  358
- Data Transfers
  358
- DMA Access
  358
- Interrupts
  360
- Duty Cycles
  375
- Dead Time
  380
- Output Control Unit
  381
- Output Enable
  381
- Output Polarity
  381
- Complementary Outputs
  382
- Crossover
  382
- Emergency Dead Time for over Modulation
  383
- Output Control Feature Precedence
  385
- Edge-Aligned Mode
  386
- Operation Modes
  386
- Waveform Modes
  386
- Center-Aligned Mode
  387
- PWM Timer Edge Aligned Update
  389
- Double Update Mode
  390
- Single Update Mode
  390
- Effective Accuracy
  391
- Synchronization of PWM Groups
  392
- Interrupts
  393
- Debug Features
  395
- Effect Latency
  395
- Emulation Considerations
  395
- Status Debug Register
  395
- Write Effect Latency
  395
- I/O Interrupt Mode
  412
- DMA Modes
  413
- Digital Application/Digital Peripheral Interfaces
  415
- Features
  416
- Register Overview
  417
- Clocking
  418
- Functional Description
  418
- DAI/DPI Signal Naming Conventions
  421
- I/O Pin Buffers
  421
- Pin Buffers as Signal Output
  422
- Pin Buffers as Signal Input
  424
- DAI/DPI Pin Buffer Status
  425
- Pin Buffers as Open Drain
  425
- Miscellaneous Buffers
  426
- Unused DAI/DPI Pins
  426
- DAI/DPI Peripherals
  428
- Output Signals with Pin Buffer Enable Control
  428
- Output Signals Without Pin Buffer Enable Control
  430
- Signal Routing Matrix by Groups
  430
- Signal Routing Units (Srus)
  430
- DAI/DPI Group Routing
  432
- Making SRU Connections
  434
- Rules for SRU Connections
  434
- Pin Buffer Enable
  440
- Pin Buffer Input
  440
- Miscellaneous Signals
  441
- DAI Default Routing
  442
- DPI Default Routing
  445
- Interrupts
  446
- System Versus Exception Interrupts
  446
- DAI Interrupt Channels
  447
- Functional Description
  447
- DAI Interrupt Priorities
  448
- DPI Interrupt Channels
  448
- DPI Interrupt Priorities
  448
- DAI Miscellaneous Interrupts
  449
- DPI Miscellaneous Interrupts
  449
- DAI/DPI Interrupt Mask Events
  450
- DAI Interrupt Acknowledge
  452
- Core Versus DAI/DPI Interrupts
  453
- DPI Interrupt Acknowledge
  453
- DAI Shadow Registers
  454
- Debug Features
  454
- DPI Shadow Registers
  454
- Loop Back Routing
  454
- Effect Latency
  456
- Programming Model
  456
- Signal Routing Unit Effect Latency
  456
- Write Effect Latency
  456
- DAI Example System
  457
- 10 Serial Ports
  459
- Features
  460
- Pin Descriptions
  462
- SRU Programming
  463
- SRU SPORT Receive Master
  464
- SRU SPORT Signal Integrity
  464
- Register Overview
  465
- Clocking
  466
- Master Clock
  466
- Master Frame Sync
  467
- Functional Description
  468
- Slave Mode
  468
- Architecture
  469
- Data Types and Companding
  470
- Transmit Path
  472
- Receive Path
  473
- Frame Sync
  474
- Frame Sync and Data Sampling
  474
- Sampling Edge
  474
- Internal Versus External Frame Syncs
  476
- Serial Word Length
  476
- External Frame Sync Sampling
  477
- Data-Independent Frame Sync
  478
- Logic Level Frame Syncs
  478
- Operation Modes
  479
- Mode Selection
  481
- Channel Order First
  482
- Standard Serial Mode
  483
- Timing Control Bits
  483
- Clocking Options
  484
- Frame Sync Options
  484
- Framed Versus Unframed Frame Syncs
  484
- Early Versus Late Frame Syncs
  485
- Left-Justified Mode
  486
- Master Serial Clock and Frame Sync Rates
  487
- Timing Control Bits
  487
- I 2 S Mode
  488
- Master Serial Clock and Frame Sync Rates
  488
- Timing Control Bits
  488
- Multichannel Mode
  489
- Clocking Options
  490
- Frame Sync Options
  490

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