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Control Register 2 Register
The
register controls HSYNC finish signal generation.
EPPI_CTL2
Figure 18-16: EPPI_CTL2 Register Diagram
Table 18-50: EPPI_CTL2 Register Fields
Bit No.
(Access)
1
FS1FINEN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
FS1FINEN (R/W)
HSYNC Finish Enable
31
30
29
0
0
Bit Name
HSYNC Finish Enable.
The EPPI_CTL2.FS1FINEN bit selects whether (if set) the EPPI sends a finish
command (010) through the DDE COMMAND line soon after a LINE is received
completely or (if cleared) the EPPI sends a finish command (010) through the DDE
COMMAND line soon after a FRAME is received completely.
Note that the EPPI_CTL.DMAFINEN bit must be set for the EPPI to generate either
of the finish commands.
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Finish sent after frame RX done. PPI sends a finish
command (010) through the DDE COMMAND line
soon after a FRAME is received completely
1 Finish sent after frame/line RX done. PPI sends a finish
command (010) through the DDE COMMAND line
soon after a frame/line is received completely.
ADSP-SC58x EPPI Register Descriptions
5
4
3
2
1
0
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
0
18–63
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