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6 Reset Control Unit (RCU)
Reset is the initial state of the whole processor at power-on or the run-time state of any core, as controlled by anoth-
er core in the device via the RCU or as a a result of a hardware or software triggered event. In this state, all control
registers are set to their default values and functional units are idle. Exiting a full system hardware reset results with
only the host core being released from reset and ready to boot (Core 0 on ADSP-SC58x devices, Core 1 on
ADSP-215xx devices). The following table shows the cores that are released from reset.
Additional information on reset and booting can be found in
Product
ADSP-SC58x
ADSP-2158x
The Reset Control Unit (RCU) controls how all the functional units enter and exit reset. Differences in functional
requirements and clocking constraints define how reset signals are generated. Programs must guarantee that none of
the reset functions puts the system into an undefined state or causes resources to stall. This functionality is impor-
tant when only one of the cores is reset (programs must ensure that there is no pending system activity involving the
core that is being reset). While core resets and software system resets are controlled directly in the RCU, hardware
resets can come from the TRU, the SEC, or the CGU Oscillator Watchdog.
RCU Features
The RCU module supports the following features:
• Hardware reset through the SYS_HWRST pin
• Software system reset through the RCU control (RCU_CTL) register
• Hardware system reset through:
• TRU module
• SEC module (System Fault Unit )
• A clock not good reset state (safe state of chip under reset) from the Oscillator Watchdog.
• Core reset through RCU Core Reset Output (RCU_CRCTL) register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Boot ROM and Booting the
Core Released from Reset by RCU
Core ID = 0
Core ID = 1
Reset Control Unit (RCU)
Processor.
6–1
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