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ADSP-SC58x CGU Register Descriptions
Oscillator Watchdog Register
The
CGU_OSCWDCTL
and provides a fault warning via the SYS_FAULT pin. The
oscillator frequencies above and below specified limits, in order to specifically detect harmonic or sub-harmonic
crystal oscillator behavior. This detection is achieved by using an internal asynchronous, local 1 MHz oscillator com-
bined with a series of programmable counters.
MONDIS (R/W)
Oscillator Watchdog Monitor functions
disabled
FAULTEN (R/W)
Fault enabled
BOUEN (R/W)
Bad Oscillator Upper Frequency limit
detection enabled
BOUF (R/W)
Bad Oscillator Upper Frequency limit
LOCK (R/W)
Lock
Figure 3-8: CGU_OSCWDCTL Register Diagram
Table 3-14: CGU_OSCWDCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
23
FAULTPINDIS
(R/W)
15
MONDIS
(R/W)
14
FAULTEN
(R/W)
13
BOUEN
(R/W)
3–24
register configures the CGU to allow the detection of the absence of input clock transitions
15
14
13
12
11
10
0
1
1
1
1
1
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Lock.
Fault Pin disabled.
The CGU_OSCWDCTL.FAULTPINDIS bit disables pin fault detection.
Oscillator Watchdog Monitor functions disabled.
The CGU_OSCWDCTL.MONDIS bit disables all the input clock monitor and fault de-
tection functions.
Fault enabled.
The CGU_OSCWDCTL.FAULTEN bit enables fault detection.
Bad Oscillator Upper Frequency limit detection enabled.
The CGU_OSCWDCTL.BOUEN bit enables upper limit bad oscillation detection.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CGU_OSCWDCTL
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
register also detects and reports input
1
0
0
0
HODF (R/W)
Watchdog lower frequency limit
HODEN (R/W)
Harmonic Oscillation Detection enabled
CNGEN (R/W)
Clock not Good enabled
17
16
0
0
FAULTPINDIS (R/W)
Fault Pin disabled
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