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3. Execute SYNC instruction.
4. Set L2CTL_CTL.ECCMAP7-L2CTL_CTL.ECCMAP0 bits of interest.
5. Execute SYNC instruction.
6. Write checksum values using 32-bit store instructions.
7. If data cache enabled, make sure that it flushes out checksum values.
8. Execute SYNC instruction.
9. Clear L2CTL_CTL.ECCMAP7-L2CTL_CTL.ECCMAP0 bits.
10. Execute SYNC instruction.
11. Read data values back.
ECC Error Management
The L2 system memory flags 2-bit and multi-bit errors to the system by:
• Raising the ECC_ERR interrupt
• Reporting a read error to the system bus
• Setting the sticky L2CTL_STAT.ECCERR7-L2CTL_STAT.ECCERR0 status flag
• Latching the address of the failing operation into the respective
register.
There is one error status bit and one error address register per L2 SRAM bank.
Typically, ECC_ERR events are declared as system faults in the system event controller (SEC). Whether these faults
are reported, the interrupt service routine can consult the
through
L2CTL_ERRADDR7
• The data at the failing L2 address was critical enough to require an immediate reboot of the system
• The data at the failing L2 address was less critical or can be restored
The L2CTL_STAT.ECCERR0 through L2CTL_STAT.ECCERR7 flags are cleared with a W1C operation.
Memory Refresh
If data in L2 SRAM contains single-bit errors, the data is corrected on its way to the system buses. The corrected
value is not written back to the SRAM location. To prevent any risk of accumulation of single-bit errors over time
and to minimize likelihood of multi-bit errors, the L2 system memory provides a special memory refresh mecha-
nism.
Software can initiate a memory refresh cycle of a 64-bit SRAM entity by writing the address of interest into the
refresh address register, L2CTL_RFA. The write triggers an atomic operation. In this operation, the L2 system
memory:
• Reads a 64-bit entity from the targeted memory
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers to determine whether:
L2CTL_ERRADDR7-L2CTL_ERRADDR0
L2CTL_STAT
register and the
Data Integrity
L2CTL_ERRADDR0
9–9
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