Analog Devices ADSP-SC58 Series Hardware Reference Manual page 227

Sharc+ processor
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ADSP-SC58x RCU Register Descriptions
Table 6-6: RCU_BCODE Register Fields (Continued)
Bit No.
(Access)
5
NOCACHE
(R/W)
4
NOMEMINIT
(R/W)
3
HBTOVW
(R/W)
2
HALT
(R/W)
1
NOVECTINIT
(R/W)
0
NOKERNEL
(R/W)
6–10
Bit Name
No Cache.
The RCU_BCODE.NOCACHE bit configures the RCU to not perform a cache initiali-
zation and to not enable the cache.
No Memory Initialization.
The RCU_BCODE.NOMEMINIT bit configures the RCU to not perform a memory
initialization.
Execute Wakeup.
The RCU_BCODE.HBTOVW bit configures the RCU to execute a wakeup.
Halt.
The RCU_BCODE.HALT bit configures the RCU to execute the no boot routine.
No Vector Initialize.
The RCU_BCODE.NOVECTINIT bit configures the RCU to not vector to the appli-
cation.
No Boot Kernel.
The RCU_BCODE.NOKERNEL bit configures the RCU to not execute the boot ker-
nel.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 Enable and initialize cache
1 Do not initialize or enable cache
0 Perform memory initialization
1 Do not perform memory initialization
0 Do not wakeup
1 Execute wakeup
0 Do not execute routine
1 Execute routine
0 Vector
1 Do not vector
0 Execute boot kernel
1 Do not execute boot kernel

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