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Manuals and User Guides for Analog Devices adsp-2100. We have 1 Analog Devices adsp-2100 manual available for free PDF download: Manual

Analog Devices adsp-2100 Manual (486 pages)

ADSP-2100 family programmable single-chip microprocessors

Brand: Analog Devices | Category: Computer Hardware | Size: 4 MB

Table of Contents
1
Chapter 1 Introduction

13
- Overview
  13
- Functional Units
  13
- Memory and System Interface
  15
- Instruction Set
  16
- DSP Performance
  16
- Core Architecture
  17
- Computational Units
  18
- Address Generators & Program Sequencer
  19
- Buses
  20
- On-Chip Peripherals
  20
- Serial Ports
  20
- Timer
  21
- Host Interface Port
  21
- DMA Ports
  21
- Analog Interface
  22
- Adsp-2100 Family Development Tools
  22
- Organization of this Manual
  23
Chapter 2 Computational Units

25
- Overview
  25
- Binary String
  25
- Unsigned
  25
- Signed Numbers: Twos-Complement
  25
- Fractional Representation: 1.15
  26
- ALU Arithmetic
  26
- MAC Arithmetic
  27
- Shifter Arithmetic
  27
- Summary
  28
- Arithmetic/Logic Unit (Alu)
  29
- ALU Block Diagram Discussion
  29
- Standard Functions
  31
- ALU Input/Output Registers
  32
- Multiprecision Capability
  32
- ALU Saturation Mode
  32
- ALU Overflow Latch Mode
  33
  - Division
    33
  - ALU Status
    37
- Multiplier/Accumulator (Mac)
  37
  - MAC Block Diagram Discussion
    37
  - MAC Operations
    40
    
    Standard Functions
    40
    
    Input Formats
    42
    
    MAC Input/Output Registers
    42
    
    MR Register Operation
    42
    
    MAC Overflow and Saturation
    43
    
    Rounding Mode
    44
    
    Biased Rounding (ADSP-217X/218X/21Msp5X)
    45
- Barrel Shifter
  46
  - Shifter Block Diagram Discussion
    46
  - Shifter Operations
    52
    
    Shifter Input/Output Registers
    52
    
    Derive Block Exponent
    53
    
    Immediate Shifts
    54
    
    Denormalize
    55
    
    Normalize
    57
Chapter 3 Program Control

61
- Overview
  61
- Program Sequencer
  61
  - Next Address Select Logic
    63
  - Program Counter & PC Stack
    64
  - Loop Counter & Stack
    64
  - Loop Comparator & Stack
    65
- Program Control Instructions
  68
  - JUMP Instruction
    68
    
    Register Indirect Jumps
    68
  - CALL Instruction
    69
  - DO until Loops
    69
  - IDLE Instruction
    70
    
    Slow IDLE
    70
- Interrupts
  71
- Status Registers & Status Stack
  80
- Conditional Instructions
  84
- Toppcstack
  85
  - TOPPCSTACK Restrictions
    87
Chapter 4 Data Transfer

89
- Overview
  89
- Data Address Generators (Dags)
  89
- Programmng Data Accesses
  95
  - Variables & Arrays
    95
  - Circular Buffers
    96
- Pmd-DMD Bus Exchange
  97
  - PMD-DMD Block Diagram Discussion
    97
Chapter 5 Serial Ports

100
- Overview
  100
- Basic Sport Description
  100
  - Interrupts
    103
  - SPORT Operation
    103
- Sport Programming
  103
  - SPORT Configuration
    104
  - Receiving and Transmitting Data
    105
- Sport Enable
  106
- Serial Clocks
  107
- Word Length
  108
- Word Framing Options
  109
  - Frame Synchronization
    110
  - Frame Sync Signal Source
    110
  - Normal and Alternate Framing Modes
    112
  - Active High or Active Low
    113
- Configuration Example
  114
- Companding and Data Format
  122
- Companding Operation Example
  123
- Contention for Companding Hardware
  124
- Companding Internal Data
  124
- Autobuffering
  125
- Autobuffering Control Register
  127
- Autobuffering Example
  127
- Multichannel Function
  129
- Multichannel Setup
  130
- Multichannel Operation
  131
- Sport Timing Considerations
  133
- Companding Delay
  133
- Clock Synchronization Delay
  133
- Startup Timing
  133
- Internally Generated Frame Sync Timing
  134
- Transmit Interrupt Timing
  135
- Receive Interrupt Timing
  136
- Interrupt and Autobuffer Synchronization
  137
- Instruction Completion Latencies
  138
- Interrupt and Autobuffer Service Example
  139
- Receive Companding Latency
  140
- Interrupts with Autobuffering Enabled
  141
- Unusual Complications
  141
Chapter 6 Timer

143
- Overview
  143
- Timer Architecture
  143
- Resolution
  145
- Timer Operation
  145
Chapter 7 Host Interface Port

147
- Overview
  147
- Hip Functional Description
  150
- Hip Operation
  152
- Polled Operation
  153
- HIP Status Synchronization
  154
- Interrupt-Driven Operation
  155
- HDR Overwrite Mode
  155
- Software Reset
  156
- Hip Interrupts
  156
- Host Interface Timing
  158
- Boot Loading through the Hip
  162
Chapter 8 Analog Interface

165
- Overview
  165
- A/D Conversion
  166
- Analog Input
  166
- Adc
  167
- Decimation Filter
  168
- High Pass Filter
  169
- D/A Conversion
  170
- Dac
  170
- High Pass Filter
  170
- Interpolation Filter
  171
- Analog Smoothing Filter & Programmable Gain Amp
  172
- Differential Output Amplifier
  172
- Operating the Analog Interface
  173
- Memory-Mapped Control Registers
  173
- Analog Control Register
  173
- Analog Autobuffer/Powerdown Register
  174
- Memory-Mapped Data Registers
  175
- ADC & DAC Interrupts
  176
- Autobuffering Disabled
  176
- Autobuffering Enabled
  177
- Circuit Design Considerations
  180
- Analog Signal Input
  180
- Analog Signal Output
  182
- Voltage Reference Filter Capacitance
  183
Chapter 9 System Interface

184
- Overview
  184
- Clock Signals
  184
- Synchronization Delay
  186
- 1X & 1/2X Clock Considerations
  186
- Reset
  187
- Software-Forced Rebooting
  188
- ADSP-2181 Register Values for BDMA Booting
  196
- External Interrupts
  197
- Interrupt Sensitivity
  197
- Flag Pins
  198
- Powerdown
  200
- Powerdown Control
  201
- Entering Powerdown
  202
- Exiting Powerdown
  203
- PWD Pin
  203
- Ending Powerdown with the RESET Pin
  204
- Startup Time after Powerdown
  204
- Systems Using an External TTL/CMOS Clock
  204
- Operation During Powerdown
  206
- Interrupts & Flags
  206
- Sports
  206
- HIP During Powerdown
  207
- IDMA Port During Powerdown (ADSP-2181)
  208
- BDMA Port During Powerdown (ADSP-2181)
  209
- Analog Interface (ADSP-21Msp5X)
  209
- Conditions for Lowest Power Consumption
  209
- PWDACK Pin
  212
- Using Powerdown as a Non-Maskable Interrupt
  213
Chapter 10 Memory Interface

214
- Overview
  214
- Program Memory Interface
  216
- External Program Memory Read/Write
  216
- Program Memory Maps
  218
- ROM Program Memory Maps
  219
- Data Memory Interface
  223
- External Data Memory Read/Write
  223
- Data Memory Maps
  224
- Memory-Mapped Peripherals
  227
- Boot Memory Interface
  228
- Boot
  228
- Powerup Boot & Software Reboot
  229
- Boot Memory Access
  230
- Boot Loading Sequence
  230
- Bus Request/Grant
  234
- Adsp-2181 Memory Interfaces
  236
- ADSP-2181 Program Memory Interface
  238
- ADSP-2181 Data Memory Interface
  243
- ADSP-2181 Byte Memory Interface
  245
- ADSP-2181 I/O Memory Space
  245
- ADSP-2181 Composite Memory Select
  248
- External Memory Read - Overlays & I/O Memory
  249
- External Memory Write - Overlays & I/O Memory
  250
- Memory Interface Summary (All Processors)
  250
Chapter 11 Dma Ports

252
- Overview
  252
- Bdma Port
  253
- BDMA Port Functional Description
  255
- BDMA Control Registers
  255
- Byte Memory Word Formats
  260
- BDMA Booting
  260
- Development Software Features for BDMA Booting
  262
- Idma Port
  263
- IDMA Port Pin Summary
  263
- IDMA Port Functional Description
  265
- Modifying Control Registers for IDMA
  267
- IDMA Timing
  268
- Address Latch Cycle
  268
- Long Read Cycle
  269
- Short Read Cycle
  271
- Long Write Cycle
  272
- Short Write Cycle
  274
- Boot Loading through the IDMA Port
  275
- DMA Cycle Stealing, DMA Hold Offs, and IACK
  276
Chapter 12 Programming Model

278
- Overview
  278
- Data Address Generators
  279
- Always Initialize L Registers
  279
- Program Sequencer
  281
- Interrupts
  281
- Loop Counts
  281
- Status and Mode Bits
  282
- Stacks
  282
- Computational Units
  283
- Bus Exchange
  283
- Timer
  283
- Serial Ports
  284
- Memory Interface & SPORT Enables
  284
- Host Interface
  285
- Analog Interface
  285
- Program Example
  285
- Example Program: Setup Routine Discussion
  287
- Example Program: Interrupt Routine Discussion
  288
Chapter 13 Hardware Examples

290
- Overview
  290
- Boot Loading from Host Using Bus Request
  291
- Serial Port to Codec Interface
  294
- Serial Port to Dac Interface
  297
- Serial Port to Adc Interface
  299
- Serial Port to Serial Port Interface
  301
- 80C51 Interface to Host Interface Port
  302
Chapter 14 Software Examples

304
- Overview
  304
- System Development Process
  305
- Single-Precision Fir Transversal Filter
  307
- Cascaded Biquad Iir Filter
  309
- Sine Approximation
  310
- Single-Precision Matrix Multiply
  312
- Radix-2 Decimation-In-Time Fft
  314
- Main Module
  314
- DIT FFT Subroutine
  316
- Bit-Reverse Subroutine
  321
- Block Floating-Point Scaling Subroutine
  322
Chapter 15 Instruction Set Reference

324
- Quick List of Instructions
  324
- Overview
  325
- Instruction Types & Notation Conventions
  326
- Multifunction Instructions
  327
- ALU/MAC with Data & Program Memory Read
  327
- Data & Program Memory Read
  329
- Computation with Memory Read
  329
- Computation with Memory Write
  329
- Computation with Data Register Move
  330
- Alu, Mac & Shifter Instructions
  332
- ALU Group
  332
- MAC Group
  333
- Shifter Group
  334
- Move: Read & Write
  335
- Program Flow Control
  337
- Miscellaneous Instructions
  339
- Extra Cycle Conditions
  341
- Multiple Off-Chip Memory Accesses
  341
- Wait States
  341
- SPORT Autobuffering & DMA
  341
- Instruction Set Syntax
  342
- Punctuation & Multifunction Instructions
  342
- Syntax Notation Example
  342
- Status Register Notation
  343
- Alu
  344
  - Subtract X-Y/Subtract X-Y with Borrow
    346
  - Subtract Y-X/Subtract Y-X with Borrow
    348
  - And, Or, Xor
    350
  - Pass/Clear
    354
  - Negate
    356
  - Not
    357
  - Absolute Value
    358
  - Increment
    359
  - Decrement
    360
  - Divide
    361
  - Generate ALU Status
    363
- MAC Multiply
  364
  - Multiply/Accumulate
    366
  - Multiply/Subtract
    368
  - Clear
    370
  - Transfer MR
    371
  - Conditional MR Saturation
    372
- Shifter
  373
  - Arithmetic Shift
    373
  - Logical Shift
    375
  - Normalize
    377
  - Derive Exponent
    379
  - Block Exponent Adjust
    381
  - Arithmetic Shift Immediate
    383
  - Logical Shift Immediate
    385
- Move
  386
  - Register Move
    386
  - Load Register Immediate
    388
  - Data Memory Read (Direct Address)
    390
  - Data Memory Read (Indirect Address)
    391
  - Program Memory Read (Indirect Address)
    392
  - Data Memory Write (Direct Address)
    393
  - Data Memory Write (Indirect Address)
    394
  - Program Memory Write (Indirect Address)
    396
  - I/O Space Read/Write
    397
- Program Flow
  398
  - Jump
    398
  - Call
    399
  - JUMP or CALL on Flag in Pin
    400
  - Modify Flag out Pin
    401
    
    Do until
    404
    
    Idle
    406
- Misc
  407
  - Stack Control
    407
  - Return from Interrupt (RTI)
    407
  - Mode Control
    410
  - Modify Address Register
    412
  - Nop
    413
  - Interrupt Enable/Disable
    414
- Multifunction
  415
  - Data & Program Memory Read
    426
    
    Instruction Coding
    430
Appendix A Instruction Coding

430
- A.1 Opcodes
  430
- Opcodes
  430
  - A.2 Abbreviation Coding
    436
  - Division Exceptions
    444
Appendix B Division Exceptions

444
- Abbreviation Coding
  436
- B.1 Division Fundamentals
  444
- Division Fundamentals
  444
- Signed Division
  444
- Output Formats
  445
- Unsigned Division
  445
- B.1.4 Integer Division
  446
- Error Conditions
  446
- Integer Division
  446
- Negative Divisor Error
  446
- Software Solution
  447
  - Numeric Formats
    452
Appendix C Numeric Formats

452
- Unsigned Division Error
  447
- C.1 Overview
  452
- Integer or Fractional
  452
- Overview
  452
- Unsigned or Signed: Twos-Complement Format
  452
- Binary Multiplication
  454
- C.4 Binary Multiplication
  454
- Fractional Mode and Integer Mode
  455
- Block Floating-Point Format
  456
  - D.1 Interrupt Vector Addresses
    458
  - Interrupt Vector Addresses
    459
  - E.1 Overview
    461

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Analog Devices adsp-2100 Manual (486 pages)

Table of Contents

Chapter 1 Introduction

Chapter 2 Computational Units

Chapter 3 Program Control

Chapter 4 Data Transfer

Chapter 5 Serial Ports

Chapter 6 Timer

Chapter 7 Host Interface Port

Chapter 8 Analog Interface

Chapter 9 System Interface

Chapter 10 Memory Interface

Chapter 11 Dma Ports

Chapter 12 Programming Model

Chapter 13 Hardware Examples

Chapter 14 Software Examples

Chapter 15 Instruction Set Reference

Appendix A Instruction Coding

Appendix B Division Exceptions

Appendix C Numeric Formats

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