Analog Devices ADSP-SC58 Series Hardware Reference Manual page 522

Table 11-12: SMC_B3CTL Register Fields (Continued)
Bit No.
(Access)
14 RDYABTEN
(R/W)
13 RDYPOL
(R/W)
12 RDYEN
(R/W)
9:8 SELCTRL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
ARDY Abort Enable.
The SMC_B3CTL.RDYABTEN bit enables the abort counter for the SMC_ARDY
pin, if enabled (SMC_B3CTL.RDYEN =1). After SMC_B3TIM.RAT or
SMC_B3TIM.WAT cycles, the SMC starts sampling the SMC_ARDY pin and starts
the abort down counter (if enabled). The abort count is 64 cycles of SCLK0_0. If the
SMC detects that SMC_ARDY remains de-asserted when the counter expires, the SMC
aborts the access and returns an error response back on the system bus.
ARDY Polarity.
The SMC_B3CTL.RDYPOL bit selects the polarity (active high or low) for the
SMC_ARDY pin, if enabled (SMC_B3CTL.RDYEN =1). When the SMC samples the
SMC_ARDY pin in the selective active state, the transaction completes.
ARDY Enable.
The SMC_B3CTL.RDYEN bit enables SMC_ARDY pin operation for bank 3 accesses.
When enabled, the SMC uses SMC_ARDY (after the access time countdown) to deter-
mine completion of access to this memory bank. When disabled, the SMC ignores
SMC_ARDY for accesses to this memory bank.
Select Control.
The SMC_B3CTL.SELCTRL bits select the handling of the SMC_AMS[n],
SMC_ARE, SMC_AOE, and SMC_AWE pins for memory access control.
ADSP-SC58x SMC Register Descriptions
Description/Enumeration
0 Disable abort counter
1 Enable abort counter
0 Low active ARDY
1 High active ARDY
0 Disable ARDY
1 Enable ARDY
0 AMS3 only
1 AMS3 ORed with ARE
2 AMS3 ORed with AOE
3 AMS3 ORed with AWE
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