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Calibration PAD Control 0 Register
The
DMC_CAL_PADCTL0
RTTCALEN (R/W)
RTT Calibration Enable
PDCALEN (R/W)
PULLDOWN Calibration Enable
Figure 10-28: DMC_CAL_PADCTL0 Register Diagram
Table 10-38: DMC_CAL_PADCTL0 Register Fields
Bit No.
(Access)
31
RTTCALEN
(R/W)
30
PDCALEN
(R/W)
29
PUCALEN
(R/W)
28
CALSTRT
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register sets the pad calibration controls.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
1
1
1
0
0
0
0
0
Bit Name
RTT Calibration Enable.
The DMC_CAL_PADCTL0.RTTCALEN bit is set to 1 at reset. Programming this bit
to 0 is not allowed.
PULLDOWN Calibration Enable.
The DMC_CAL_PADCTL0.PDCALEN bit is set to 1 at reset. Programming this bit
to 0 is not allowed.
PULLUP Calibration Enable.
The DMC_CAL_PADCTL0.PUCALEN bit is set to 1 at reset. Programming this bit
to 0 is not allowed.
Start New Calibration ( Hardware Cleared).
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
CALSTRT (R/W)
Start New Calibration ( Hardware Cleared)
PUCALEN (R/W)
PULLUP Calibration Enable
10–69
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