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ADSP-SC58x UART Register Descriptions
Control Register
The
register provides enable and disable control for internal UART and for the IrDA mode of opera-
UART_CTL
tion. This register also provides UART line control, permitting selection of the format of received and transmitted
character frames. Modem feature control also is available from this register, including partial modem functionality to
allow for hardware flow control and loopback mode.
EPS (R/W)
Even Parity Select
PEN (R/W)
Parity Enable
STBH (R/W)
Stop Bits (Half Bit Time)
STB (R/W)
Stop Bits
RFRT (R/W)
Receive FIFO RTS Threshold
RFIT (R/W)
Receive FIFO IRQ Threshold
ACTS (R/W)
Automatic CTS
ARTS (R/W)
Automatic RTS
XOFF (R/W)
Transmitter off
MRTS (R/W)
Manual Request to Send
TPOLC (R/W)
IrDA TX Polarity Change
Figure 17-12: UART_CTL Register Diagram
17–26
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
EN (R/W)
Enable UART
LOOP_EN (R/W)
Loopback Enable
MOD (R/W)
Mode of Operation
WLS (R/W)
Word Length Select
STP (R/W)
Sticky Parity
FPE (R/W)
Force Parity Error on Transmit
FFE (R/W)
Force Framing Error on Transmit
SB (R/W)
Set Break
FCPOL (R/W)
Flow Control Pin Polarity
RPOLC (R/W)
IrDA RX Polarity Change
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