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Receive Shift Register
The read only
UART_RSR
The frame data is moved into this shift register after polarity inversion, if any (including the native polarity inversion
in the IrDA case).
In the case of the longest frame (MDB, with parity mode, and 8 bit data word-length), the start bit may be shifted
out and not available for reading at the end of the frame reception. This register is NOT reset at the start of frame.
If read, in the middle of a frame reception, data corresponding the previous frame may not have entirely shifted out
(for example, the read data that have been read may NOT correspond entirely to the frame being received).
Because the UART is receiving only 1 stop bit, the
bit is present in the actual transfer. This register may be considered as storing the 10 most recently received bits
(taking into consideration the stop bit receive limitation above).
Figure 17-17: UART_RSR Register Diagram
Table 17-16: UART_RSR Register Fields
Bit No.
(Access)
9:0
VALUE
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register which returns the content of the UART's receive shift register.
15
14
13
12
0
0
0
VALUE (R)
Contents of RSR
31
30
29
28
0
0
0
Bit Name
Contents of RSR.
UART_RSR
contains only 1 stop bit even if more than one stop
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x UART Register Descriptions
4
3
2
1
0
0
0
0
0
0
19
18
17
16
0
0
0
0
0
17–41
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