Analog Devices ADSP-SC58 Series Hardware Reference Manual page 45

Peripheral Mode, Bulk IN, Transfer Size Unknown ......................................................................... 27–27
Peripheral Mode, ISO IN, Small MaxPktSize................................................................................... 27–28
Peripheral Mode, ISO IN, Large MaxPktSize .................................................................................. 27–28
Peripheral Mode, Bulk OUT, Transfer Size Known.......................................................................... 27–29
Peripheral Mode, Bulk OUT, Transfer Size Unknown...................................................................... 27–29
Peripheral Mode, ISO OUT, Small MaxPktSize............................................................................... 27–30
Peripheral Mode, ISO OUT, Large MaxPktSize............................................................................... 27–30
Peripheral Mode Suspend .................................................................................................................... 27–31
Start of Frame (SOF) Packets .............................................................................................................. 27–31
Soft Connect/Soft Disconnect ............................................................................................................. 27–31
Error Handling As a Peripheral ........................................................................................................... 27–31
Stalls Issued to Control Transfers ........................................................................................................ 27–32
Zero Length OUT Data Packets in Control Transfers ......................................................................... 27–33
Host Mode ............................................................................................................................................. 27–33
Transaction Scheduling ....................................................................................................................... 27–33
Endpoint Setup and Data Transfer ...................................................................................................... 27–34
Control Transaction as a Host ............................................................................................................. 27–34
Set up Phase as a Host......................................................................................................................... 27–34
IN Data Phase as a Host ..................................................................................................................... 27–35
OUT Data as a Host (Control) ........................................................................................................... 27–36
IN Status Phase as a Host (Following SETUP Phase or OUT Data Phase) ......................................... 27–36
OUT Status Phase as a Host (Following IN Data Phase) .................................................................... 27–37
Host IN Transactions .......................................................................................................................... 27–38
Host OUT Transactions...................................................................................................................... 27–38
Multi-Point Support ........................................................................................................................... 27–39
Allocating Devices to Endpoints ...................................................................................................... 27–39
Multi-Point Operation .................................................................................................................... 27–40
Multi-Point Bandwidth Considerations ........................................................................................... 27–41
Babble Interrupt.................................................................................................................................. 27–41
VBUS Events....................................................................................................................................... 27–41
Actions as an A Device ..................................................................................................................... 27–42
Actions as a B Device ....................................................................................................................... 27–42
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xlv