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DMA SAR High Read Channel Register ............................................................................................. 29–136
DMA SAR Low Read Channel Register ............................................................................................... 29–137
DMA Transfer Size Read Channel Register ......................................................................................... 29–138
DMA Write Abort IMWr Address High Register ................................................................................. 29–139
DMA Write Abort IMWr Address Low Register .................................................................................. 29–140
DMA Write Channel Arbitration Weight Low Off Register ................................................................. 29–141
DMA Write Channel 1 and 0 IMWr Data Register ............................................................................. 29–142
DMA Control 1 Write Channel Register ............................................................................................. 29–143
DMA Dar High Write Channel Register ............................................................................................. 29–146
DMA DAR Low Write Channel Register ............................................................................................. 29–147
DMA Write Done IMWr Interrupt Address High Register .................................................................. 29–148
DMA Write Done IMWr Address Low Register .................................................................................. 29–149
DMA Write Doorbell Register ............................................................................................................. 29–150
DMA Write Engine Enable Register .................................................................................................... 29–151
DMA Write Error Status Register ........................................................................................................ 29–152
DMA Write Interrupt Clear Register ................................................................................................... 29–153
DMA Write Interrupt Mask Register ................................................................................................... 29–154
DMA Write Interrupt Status Register .................................................................................................. 29–155
DMA LLP High Write Channel Register ............................................................................................. 29–156
DMA LLP Low Write Channel Register .............................................................................................. 29–157
DMA Write Linked List Error Enable Register .................................................................................... 29–158
DMA Write Posted Request Deadlock Timer Register ......................................................................... 29–159
DMA SAR High Write Channel Register ............................................................................................ 29–160
DMA SAR Low Write Channel Register .............................................................................................. 29–161
DMA Transfer Size Write Channel Register ......................................................................................... 29–162
DMA Number of Channels Register .................................................................................................... 29–163
DMA Channel Context Index Register ................................................................................................ 29–164
Endpoint Base Address Mask Register 0 .............................................................................................. 29–165
Endpoint Base Address Register 0 ........................................................................................................ 29–166
Endpoint Base Address Mask Register 1 .............................................................................................. 29–167
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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Table of Contents
