Analog Devices ADSP-SC58 Series Hardware Reference Manual page 234

Table 6-10: RCU_MSG Register Fields (Continued)
Bit No.
(Access)
24 HALTONAPP
(R/W)
22 L2INIT
(R/W)
21 SECINIT
(R/W)
20 C2ACTIVATE
(R/W)
19 C1ACTIVATE
(R/W)
18 C2L1INIT
(R/W)
17 C1L1INIT
(R/W)
16 C0L1INIT
(R/W)
10 C2IDLE
(R/W)
9 C1IDLE
(R/W)
8 C0IDLE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Halt on Application Call.
The RCU_MSG.HALTONAPP bit generates an emulation exception prior to an appli-
cation call.
L2 Initialized.
The RCU_MSG.L2INIT bit indicates that the L2 resource is initialized.
SEC Initialized.
The RCU_MSG.SECINIT bit is used by tools for initialization of the SEC.
Core 2 Activated.
The RCU_MSG.C2ACTIVATE bit is used by tools for activation of Core 2.
Core 1 Activated.
The RCU_MSG.C1ACTIVATE bit is used by tools for activation of Core 1.
Core 2 L1 Initialized.
The RCU_MSG.C2L1INIT bit indicates that the core 2 L1 resource is initialized.
Core 1 L1 Initialized.
The RCU_MSG.C1L1INIT bit indicates that the core 1 L1 resource is initialized.
Core 0 L1 Initialized.
The RCU_MSG.C0L1INIT bit indicates that the core 0 L1 resource is initialized.
Core 2 Idle.
The RCU_MSG.C2IDLE bit indicates that core 2 is in a safe idle state in ROM.
Core 1 Idle.
The RCU_MSG.C1IDLE bit indicates that core 1 is in a safe idle state in ROM.
Core 0 Idle.
The RCU_MSG.C0IDLE bit indicates that core 0 is in a safe idle state in ROM.
ADSP-SC58x RCU Register Descriptions
Description/Enumeration
0 Do not generate exception
1 Generate exception
0 Resource not initialized
1 Resource initialized
0 Resource not initialized
1 Resource initialized
0 Resource not initialized
1 Resource initialized
6–17