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15 Link Port (LP)
Link ports allow the processor to connect to other processors or peripheral link ports using a simple communication
protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnection schemes
to I/O peripheral devices as well as co-processing and multiprocessing schemes.
The link ports of the processor support 8-bit wide data transfers. The link port pins are multiplexed in the GPIO
ports. For information on processor multiplexing, see the data sheet for the specific processor.
Link ports can operate independently and simultaneously, allowing glueless high-speed connectivity of up to four
external processors.
LP Features
All link ports are identical in their design and have the following common features.
• Bidirectional ports with eight data signals (LP0_D0 - LP0_D7), an acknowledge signal (LP0_ACK), and a
clock signal (LP0_CLK).
• Provide high-speed, point-to-point data transfers to other processors, allowing different types of interconnec-
tions between multiple processors.
• Pack data into 32-bit words. The processor can directly read this data or transfer it through DMA to or from
on-chip memory.
• Support for data buffering through a 2-deep FIFO for transmit and a 4-deep FIFO for receive.
• Programmable clock and acknowledge based handshake mechanism for efficient communication.
• A dedicated DMA channel.
LP Functional Description
This section provides a description of the link port, including a list of its registers and a functional block diagram.
ADSP-SC58x LP Register List
The Link Port LP is an 8-bit wide parallel port that can connect to another processor's LP or another LP-compatible
device. This port allows a variety of interconnection schemes to I/O peripheral devices as well as co-processing and
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Link Port (LP)
15–1
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