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ADSP-SC58x LP Register Descriptions
Clock Divider Value Register
The
register selects the divisor for ratio between the internal LP clock (LCLK) and system clock
LP_DIV
(CDU0_CLKO8). This programming is applicable only for the transmitter. The receiver can operate at any asyn-
chronous frequency up to the maximum frequency independent of the ratio programmed.
Figure 15-14: LP_DIV Register Diagram
Table 15-8: LP_DIV Register Fields
Bit No.
(Access)
7:0
VALUE
(R/W)
15–20
15
14
13
0
0
0
VALUE (R/W)
Divisor Value
31
30
29
0
0
0
Bit Name
Divisor Value.
The LP_DIV.VALUE bits select the clock divider (relating the LP' internally generat-
ed clock (LCLK) to the system clock (CDU0_CLKO8). The LP_DIV.VALUE
should be programmed prior to LP enable.
For LP_DIV.VALUE = 0, LCLK = CDU0_CLKO8
For LP_DIV.VALUE = xxxxxxxx, LCLK = CDU0_CLKO8 / (2 x DIV)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
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