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SMPU Control Register
The
register provides access to the locking control, error interrupts and SMPU violations.
SMPU_CTL
RLOCK (R/W)
RCTLn, RADDRn, RIDxn and RIDMxn
Registers Lock Bit
PINTEN (R/W)
Protection Violation Interrupt Enable
PBETYPE (R/W)
Protection Violation Bus Error Type
LOCK (R/W)
Lock Bit
Figure 13-4: SMPU_CTL Register Diagram
Table 13-8: SMPU_CTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
4
RLOCK
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Lock Bit.
When the SMPU_CTL.LOCK bit is set and the global lock signal is asserted from the
SPU, the
when the global lock signal becomes deasserted again.
RCTLn, RADDRn, RIDxn and RIDMxn Registers Lock Bit.
When the SMPU_CTL.RLOCK bit is set, all the registers associated with region-based
control (SMPU_RCTL[n], SMPU_RADDR[n], SMPU_RIDA[n],
SMPU_RIDB[n],
tected when the global lock signal is active from the SPU. Write access is allowed again
when the global lock signal is deasserted.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
SMPU_CTL
register is write-protected. Write-protection is disabled only
0 CTL Global Lock Disable. The
not write-protected.
1 CTL Global Lock Enable. The
write-protected.
SMPU_RIDMSKA[n]
0 Region Registers Write-Protect Enable. All region regis-
ters are not write-protected.
1 Region Registers Write-Protect Disable. All region regis-
ters are write-protected.
ADSP-SC58x SMPU Register Descriptions
RSDIS (R/W)
Read Speculation Disable
PBEDIS (R/W)
Protection Violation Bus Error Disable
SMPU_CTL
SMPU_CTL
and SMPU_RIDMSKB[n]) are write-pro-
register is
register is
13–17
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