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(PWM_CHA_DT
through PWM_CHD_DT). The unit in this case produces active low signals so that a low level corre-
sponds to a command to turn-on the associated power device.
The Dead Time Between Outputs in Dependent Mode figure shows a typical pair of PWM outputs, PWM_AH and
PWM_AL. The time values in the figure indicate the integer value in the associated register and can be converted to
time by multiplying by the fundamental time increment, t
PWM_TM0.
In the example, the pulse mode is set to 00 so that the switching patterns are perfectly symmetrical about the mid-
point of the switching period. The dead time is incorporated by moving the switching instants of both PWM signals
away from the instant set by the
t
) to preserve the symmetrical output patterns. Also shown is the PWM_SYNC output pulse whose rising edge
CK
denotes the beginning of the switching period, and the PWM_STAT.TMR0PHASE bit.
Figure 19-15: Dead Time Between Outputs in Dependent Mode
The PWM timing unit produces the resulting on-times (active low) of the PWM signals over the full PWM period
(two half-periods). The figure illustrates this timing. The timing can be written per the following equation.
T
=
(PWM_TM0
+ 2 ×
AH
Range of T
is [0:2 ×
AH
T
=
(PWM_TM0
− 2 ×
AL
Range of T
is [0:2 ×
PWM_TM0
AL
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_AH0
register. Both switching edges are moved by an equal amount (DT ×
+PWM_TM/2
COUNT
PWM_CH0
PWM_AH
PWM_AL
2 × DT
PWM_SYNC_OUT
PWM_PHASE
(PWM_AH0
− PWM_CH[x]_DT)) × t
× t
]
PWM_TM0
CK
(PWM_AH0
+ PWM_CH[x]_DT)) × t
× t
]
CK
=
d
AH
=
d
AL
. In the example, channel A is working from
CK
-PWM_TM/2
0
0
PWM_TM
PWM_TM
CK;
CK;
T
1
PWM_AH0
−
DT
=
+
AH
Ts
2
PWM_TM
+
T
1
PWM_AH0
DT
=
AL
−
Ts
2
PWM_TM0
Channel Timing Control Unit
+PWM_TM/2
PWM_CH0
2 × DT
19–21
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