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ADSP-SC58x RCU Register Descriptions
Core Reset Outputs Status Register
The RCU core reset status register (RCU_CRSTAT) contains status bits, indicating which core reset signals have
been asserted.
Figure 6-3: RCU_CRSTAT Register Diagram
Table 6-8: RCU_CRSTAT Register Fields
Bit No.
(Access)
2:0
CR[n]
(R/W1C)
6–12
15
14
13
0
0
0
CR[n] (R/W1C)
Core Reset Outputs
31
30
29
0
0
0
Bit Name
Core Reset Outputs.
The RCU_CRSTAT.CR[n] bits indicate which cores have been reset since the last
time the bit was cleared. Bits masked by CORE_DISABLE_MASK[15:0] are perma-
nently disabled and the corresponding CR bits set. CR bits are sticky, they need to be
cleared by software.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 RCU_CRES[1:0] deasserted. CR[n] corresponds to
RCU_CRES[n].
7 RCU_CRES[2:0] were asserted since the last time bits
were cleared. CR[n] corresponds to RCU_CRES[n].
4
3
2
1
0
0
0
1
1
0
20
19
18
17
16
0
0
0
0
0
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