Analog Devices ADSP-SC58 Series Hardware Reference Manual page 870

1. Provide active data frame in memory.
2. Set the EPPI_CTL.BLANKGEN bit so the EPPI generates blanking information.
3. Configure the EPPI_FS1_WLHB, EPPI_FS1_PASPL, EPPI_FS2_WLVB,
accordingly.
4. Configure the rest of the EPPI settings.
5. Configure DMA to fetch active frame data from memory buffers.
6. Enable DMA.
7. Enable the EPPI.
8. To program the EPPI in internal clock mode, follow the procedure above with the EPPI_CTL.ICLKGEN bit
=0. After enabling the EPPI, add a delay of 200 SCLK1_0 cycles (worst case) to ensure the EPPI FIFO be-
comes full. Then switch to internal clock mode by setting the EPPI_CTL.ICLKGEN bit =1.
The EPPI takes the active data from memory, generates the blanking information, and transmits an ITU-R 656
frame
Configuring Transfers in GP 0 FS Mode
The EPPI can be configured to not use periodic frame syncs to frame the data.
1. Configure the EPPI to operate in GP 0 FS mode by setting EPPI_CTL.XFRTYPE = b#11 and
EPPI_CTL.FSCFG = b#00.
2. When receiving, configure the EPPI to trigger on internally or externally by setting the EPPI_CTL.FLDSEL
field appropriately. When transmitting, the EPPI always generates a trigger internally.
3. Configure DMA to move the data to or from memory.
4. Enable DMA.
5. Enable EPPI.
6. To program the EPPI in internal clock mode, follow the procedure above with the EPPI_CTL.ICLKGEN bit
=0. After enabling the EPPI, add a delay of 200 SCLK1_0 cycles (worst case) to ensure the EPPI FIFO be-
comes full. Then switch to internal clock mode by setting the EPPI_CTL.ICLKGEN bit =1.
The DMA descriptions control the amount of data transferred. The frame syncs from the EPPI do not control the
amount.
Configuring Transfers in GP 1 FS Mode
The GP 1 FS mode is useful for interfacing the EPPI with analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and other general-purpose devices. This mode works for both transmit and receive.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
EPPI Programming Model
EPPI_FS2_PALPF registers
18–31