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Unused DAI Connections.......................................................................................................................... 33–18
DAI Operating Modes ............................................................................................................................... 33–18
DAI Pin Buffer Polarity.......................................................................................................................... 33–18
DAI Miscellaneous Buffer Polarity ......................................................................................................... 33–18
DAI System Interrupt Controller (SIC) ..................................................................................................... 33–19
Signal Routing Unit Effect Latency............................................................................................................ 33–21
DAI Programming Model.......................................................................................................................... 33–21
Debug Features .......................................................................................................................................... 33–21
DAI Sources Overview............................................................................................................................... 33–22
DAI0 Group A – Clock Routing Source Signals ..................................................................................... 33–22
DAI0 Group B – Serial Data Source Signals ........................................................................................... 33–23
DAI0 Group C – Frame Sync Source Signals .......................................................................................... 33–25
DAI0 Group D – Pin Signal Assignment Source Signals ........................................................................ 33–26
DAI0 Group E – Miscellaneous Source Signals ...................................................................................... 33–29
DAI0 Group F – Pin Output Enable Source Signals .............................................................................. 33–31
DAI1 Group A – Clock Routing Source Signals ..................................................................................... 33–32
DAI1 Group B – Serial Data Source Signals ........................................................................................... 33–34
DAI1 Group C – Frame Sync Source Signals .......................................................................................... 33–35
DAI1 Group D – Pin Signal Assignment Source Signals ........................................................................ 33–37
DAI1 Group E – Miscellaneous Source Signals ...................................................................................... 33–40
DAI1 Group F – Pin Output Enable Source Signals .............................................................................. 33–41
DAI Destination Registers Overview ......................................................................................................... 33–43
ADSP-SC58x DAI Register Descriptions .................................................................................................. 33–49
Clock Routing Control Register 0 ......................................................................................................... 33–52
Clock Routing Control Register 1 ......................................................................................................... 33–54
Clock Routing Control Register 2 ......................................................................................................... 33–56
Clock Routing Control Register 3 ......................................................................................................... 33–57
Clock Routing Control Register 4 ......................................................................................................... 33–58
Clock Routing Control Register 5 ......................................................................................................... 33–59
Serial Data Routing Control Register 0 ................................................................................................. 33–60
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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