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ADSP-SC58x SEC Register Descriptions
Global Control Register
The SEC global control register (SEC_GCTL) provides register locking, reset, and enable for the SEC module.
RESET (R0/W)
Reset
Figure 7-25: SEC_GCTL Register Diagram
Table 7-24: SEC_GCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
1
RESET
(R0/W)
0
EN
(R/W)
7–50
15
14
13
12
0
0
0
0
31
30
29
28
0
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the SEC_GCTL.LOCK
bit is enabled, the
Reset.
The SEC_GCTL.RESET bit is write-1-action and triggers a soft reset to all SEC reg-
isters.
Enable.
The SEC_GCTL.EN bit is read/write and must be set for the SEC to begin/resume
SEC operation with the current configuration and status. Clearing the
SEC_GCTL.EN bit halts the execution of the SFI and all SCIs. All SSIs remain active,
along with all error detection, without resetting status registers.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
11
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
Description/Enumeration
SEC_GCTL
register is read only.
0 Unlock
1 Lock
0 No Action
1 Reset
0 Disable
1 Enable
3
2
1
0
0
0
0
0
EN (R/W)
Enable
19
18
17
16
0
0
0
0
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