Analog Devices ADSP-SC58 Series Hardware Reference Manual page 728

Memory-Mapped Mode (SPI2 only)
SSEL
SCK
MOSI
(Q0)
MISO
(Q1)
Q2
Q3
M = 1, 2, 3, 4 ADDRESS BYTES
N = 4, 8, 16, 32 READ DATA BYTES
Z = 0, 2, 4, 6, 8, 12, 14 BUS TURN AROUND CYCLES
* = 4 DATA BITS ARE SENT PER CLOCK PERIOD ON Q<3:0>
Figure 16-19: SPI Flash Quad I/O Read Sequence
SPI memory-mapped reads can be made cacheable in the core's internal memory by properly configuring the region
as cacheable memory without bypass (see the related core's cache configuration documentation for details). In the
figures, the number of read data bytes (N) is based on the following:
• For an instruction fetch by core (when in XIP mode); the number of instruction bytes to fetch depends the
cache line size of the cache.
• For a data fetch by the core (data read), the number of data bytes to fetch depends on the cache line size of the
cache.
Although the minimum size of a memory-mapped data read transfer is 4 bytes, applications can fetch a single byte
or a 2-byte data. (For example, it can fetch an unsigned char or short access in C code). In this case, only the re-
quired bytes are provided to the core and the other bytes are cached.
The on-chip memory subsystem master provides a starting address for the burst and the SPI hardware issues this
address as part of the read header. The address provided is N-byte aligned. For example, to read the 30th byte from
SPI memory, then the typical address to provide is:
• 28 (0x0000_001C) for a 32-bit cache line
• 24 (0x0000_0018) for a 64-bit cache line
• 16 (0x0000_0010) for a 128-bit cache line
• 0 (0x0000_0000) for a 256-bit cache line
The read data is returned to the memory subsystem in the order provided by the SPI memory. There can be consid-
erable delay for the expected data provided to the master.
16–22
READ CMD ADDRESS
1 BYTE M BYTES
ADDRESS
M BYTES
ADDRESS
M BYTES
ADDRESS
M BYTES
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
CONTINUOUS
CLOCKING
Z
HI-Z
MODE READ DATA
BITS N BYTES (*)
HI-Z
MODE READ DATA
BITS N BYTES (*)
HI-Z
MODE READ DATA
BITS N BYTES (*)
HI-Z
MODE READ DATA
BITS N BYTES (*)
N x 2
CLOCKS