Analog Devices ADSP-SC58 Series Hardware Reference Manual page 92

Security Packet Engine (PKTE)
PKTE Features............................................................................................................................................. 44–1
PKTE Functional Description ..................................................................................................................... 44–1
ADSP-SC58x PKTE Register List ............................................................................................................ 44–1
ADSP-SC58x PKTE Interrupt List ......................................................................................................... 44–3
PKTE Definitions .................................................................................................................................... 44–4
Cipher Module ......................................................................................................................................... 44–5
Hash Module............................................................................................................................................ 44–5
Pseudo-Random Number Generator ........................................................................................................ 44–6
Packet Engine Processing Details.............................................................................................................. 44–8
Crypto Padding ..................................................................................................................................... 44–8
Pad Generation and Insertion ............................................................................................................ 44–9
Pad Types........................................................................................................................................... 44–9
Pad Length....................................................................................................................................... 44–10
Pad Verification and Consumption .................................................................................................. 44–12
Crypto and Hash Algorithms .............................................................................................................. 44–14
IV Processing....................................................................................................................................... 44–17
ARC4 Processing................................................................................................................................. 44–18
Hash State Loading ............................................................................................................................. 44–19
Sequence Number Processing .............................................................................................................. 44–19
Sequence Number Processing in Extended SSL/TLS........................................................................ 44–19
Sequence Number Processing in DTLS............................................................................................ 44–20
PKTE Block Diagram............................................................................................................................. 44–23
PKTE Architectural Concepts ................................................................................................................ 44–24
Packet Engine...................................................................................................................................... 44–24
Input/Output FIFO Buffers ................................................................................................................ 44–25
Parallel Operations .............................................................................................................................. 44–25
DMA Controller ................................................................................................................................. 44–25
Interrupt Controller ............................................................................................................................ 44–25
Clock Controller ................................................................................................................................. 44–25
PKTE Operating Modes ............................................................................................................................ 44–26
xcii ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference