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SMC Functional Description
ADSP-SC58x SMC Register List
The Static Memory Controller SMC is a protocol converter and data transfer interface between the internal process-
or bus and the external L3 memory. The SMC acts as a bus slave, and accesses to SMC are arbitrated by the mod-
ule's system crossbar. On the chip boundary, the SMC is connected to an external memory address bus, a 16‐bit
data bus and memory control signal pins (read, write, select). This memory interface can support a sizable external
memory connected to one or more banks, each bank being controlled by a chip select signal. A set of registers gov-
erns SMC operations. For more information on SMC functionality, see the SMC register descriptions. For the
memory map, see the product data sheet.
Table 11-1: ADSP-SC58x SMC Register List
Name
SMC_B0CTL
SMC_B0ETIM
SMC_B0TIM
SMC_B1CTL
SMC_B1ETIM
SMC_B1TIM
SMC_B2CTL
SMC_B2ETIM
SMC_B2TIM
SMC_B3CTL
SMC_B3ETIM
SMC_B3TIM
SMC Architectural Concepts
The SMC can support connection to multiple different external banks, with each bank controlled by the
SMC_AMS[n] chip select signal. Check the processor data sheet for details on the bank address ranges and configu-
rations.
NOTE:
The processor data sheet shows the address range allocated to each bank. It is not necessary to populate all
of an enabled memory bank.
The processor does not directly support 8-bit accesses to the external memories. So, the SMC address lines start
from SMC_A01; there is no SMC_A0 pin.
The SMC does indirectly support 8-bit accesses through the additional byte enable signals SMC_ABE0 and
SMC_ABE1. Some 16-bit memory systems allow the processor to perform 8-bit reads and writes, which are selected
through the SMC_ABE0 and SMC_ABE1 signals.
11–4
Description
Bank 0 Control Register
Bank 0 Extended Timing Register
Bank 0 Timing Register
Bank 1 Control Register
Bank 1 Extended Timing Register
Bank 1 Timing Register
Bank 2 Control Register
Bank 2 Extended Timing Register
Bank 2 Timing Register
Bank 3 Control Register
Bank 3 Extended Timing Register
Bank 3 Timing Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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