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Status Information Register
The TRU status register (TRU_STAT) contains the status of
tus of bus read/write errors.
ADDRERR (R/W1C)
Address Error Status
Figure 8-6: TRU_STAT Register Diagram
Table 8-10: TRU_STAT Register Fields
Bit No.
(Access)
1
ADDRERR
(R/W1C)
0
LWERR
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Address Error Status.
The TRU_STAT.ADDRERR bit is set when an invalid address is provided for an
MMR access while the TRU is selected. Writing a one to this bit clears the error indi-
cation. The
ing an MMR access while the TRU is selected.
Lock Write Error Status.
If TRU_STAT.LWERR is set, a lock write error has occurred. Writing a one to this bit
clears the error indication.
and
TRU_MTR
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
TRU_ERRADDR
register also is updated when an address error occurs dur-
0 No error
1 Error occurred
0 No error
1 Error occurred
ADSP-SC58x TRU Register Descriptions
register writes and sta-
TRU_SSR[n]
1
0
0
0
LWERR (R/W1C)
Lock Write Error Status
17
16
0
0
8–21
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