Analog Devices ADSP-SC58 Series Hardware Reference Manual page 375

ARM and eight banks of L2 RAM containing 32 Kbytes each. ARM's 0x00000000 location (reset ISR) is mapped
to this block. The L2CTL1 block contains one bank of boot ROM for SHARC+ ID = 1 and eight banks of applica-
tion ROM.
ARM A5
L1 CACHE
L2CACHE
LEGEND:
S1/S2-Ports: SHARC+ S1/S2 slave ports
D-Port: SHARC+ master data port
I-Port: SHARC+ master instruction port
Figure 9-1: ADSP-SC58x Complete L2 System Block Diagram
L2 System Memory Architectural Concepts
The following sections describe architecture features of the L2 system memory.
•
Read/Write Latency and Throughput
•
Arbitration and Priority
Access Characteristics
The L2 system memory interface converts all 8-bit, 16-bit, and 32-bit accesses to 64-bit accesses. Additionally, it
converts 8-bit, 16-bit, and 32-bit bursts to an equivalent internal 64-bit access. For example, the L2 system memory
interface converts a 64-bit address-aligned burst of 8-bit accesses of burst length 8 to a single 64-bit access.
Read/Write Latency and Throughput
The L2 memory design is optimized for burst accesses at the crossbar interface. The L2 system memory buffers and
converts write data of 8/16/32-bit to an equivalent 64-bit access. This conversion creates modulo-32-bit writes if the
starting addresses are 32-bit aligned. A single 8-bit or 16-bit access, or a non-32-bit address-aligned 8-bit or 16-bit
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
32
S1-PORT
SHARC+ ID=1
64
D-PORT
64
SHARC
D-PORT
ONLY
64
SMPU
PORT0
2 MBITS RAM +
SRAM 0.25 MBITS ROM
(RAM + ARMBOOT ROM)
PORT1
SMPU
L2CTL0
32
32
DMA ENGINES
32 32
S2-PORT S1-PORT
SHARC+ ID=2
I-PORT D-PORT
64 64
CORE FABRIC
64
SMPU
SMPU
PORT0 PORT0
2 MBITS ROM +
0.25 MBITS ROM
ROM2
ROM1
(SHARC+ 1 & 2 CODE
& BOOT ROM)
PORT1
PORT1
SMPU SMPU
L2CTL1
32
SYSTEM FABRIC
64 64
DMC0 DMC1 ......... sMMR
L2 System Memory Functional Description
32
S2-PORT
I-PORT
64
32
64
64
2 MBITS ROM +
0.25 MBITS ROM
(SHARC+ 1 & 2
CODE ROM)
L2CTL2
32
32
9–3