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PINT Edge Clear Register
The
PINT_EDGE_CLR
PINT_EDGE_CLR
enables level sensitivity for the corresponding pin interrupt.
PIQ15 (R/W1C)
Pin Interrupt 15 Level
PIQ14 (R/W1C)
Pin Interrupt 14 Level
PIQ13 (R/W1C)
Pin Interrupt 13 Level
PIQ12 (R/W1C)
Pin Interrupt 12 Level
PIQ11 (R/W1C)
Pin Interrupt 11 Level
PIQ10 (R/W1C)
Pin Interrupt 10 Level
PIQ9 (R/W1C)
Pin Interrupt 9 Level
PIQ8 (R/W1C)
Pin Interrupt 8 Level
PIQ31 (R/W1C)
Pin Interrupt 31 Level
PIQ30 (R/W1C)
Pin Interrupt 30 Level
PIQ29 (R/W1C)
Pin Interrupt 29 Level
PIQ28 (R/W1C)
Pin Interrupt 28 Level
PIQ27 (R/W1C)
Pin Interrupt 27 Level
PIQ26 (R/W1C)
Pin Interrupt 26 Level
PIQ25 (R/W1C)
Pin Interrupt 25 Level
PIQ24 (R/W1C)
Pin Interrupt 24 Level
Figure 14-26: PINT_EDGE_CLR Register Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register permits selecting level-sensitive interrupts. Writing 1 to a bit in
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
ADSP-SC58x PINT Register Descriptions
1
0
0
0
PIQ0 (R/W1C)
Pin Interrupt 0 Level
PIQ1 (R/W1C)
Pin Interrupt 1 Level
PIQ2 (R/W1C)
Pin Interrupt 2 Level
PIQ3 (R/W1C)
Pin Interrupt 3 Level
PIQ4 (R/W1C)
Pin Interrupt 4 Level
PIQ5 (R/W1C)
Pin Interrupt 5 Level
PIQ6 (R/W1C)
Pin Interrupt 6 Level
PIQ7 (R/W1C)
Pin Interrupt 7 Level
17
16
0
0
PIQ16 (R/W1C)
Pin Interrupt 16 Level
PIQ17 (R/W1C)
Pin Interrupt 17 Level
PIQ18 (R/W1C)
Pin Interrupt 18 Level
PIQ19 (R/W1C)
Pin Interrupt 19 Level
PIQ20 (R/W1C)
Pin Interrupt 20 Level
PIQ21 (R/W1C)
Pin Interrupt 21 Level
PIQ22 (R/W1C)
Pin Interrupt 22 Level
PIQ23 (R/W1C)
Pin Interrupt 23 Level
14–73
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