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ADSP-SC58x PORT Register Descriptions
Port x GPIO Direction Register
The PORT_DIR, PORT_DIR_SET, and
registers select output or input mode for GPIO pins
PORT_DIR_CLR
and enable output drivers. Use the PORT_INEN, PORT_INEN_SET, and
PORT_INEN_CLR
registers to enable
or disable input drivers.
Writes to the
PORT_DIR
register affect the state of all pins of the port. To select a direction for specific pins with-
out impacting other pins of the port, use the
and
registers.
PORT_DIR_SET
PORT_DIR_CLR
Setting a bit in the
register enables output mode on the corresponding a GPIO pin. Clearing a bit in
PORT_DIR
the
PORT_DIR
register disables output mode on the corresponding GPIO pin.
Input Mode - The default mode of every GPIO pin after reset is the input mode, but the input drivers are not
enabled. To enable GPIO input drivers, set the corresponding bits in the
PORT_INEN
register. When enabled, a
read from the
register returns the logical state of the input pin. The input signal does not overwrite
PORT_DATA
the state of the bit used for the output case. That state can only be altered by software. If the input driver is enabled,
a write to the
PORT_DATA
register can alter the state of the bit, but the change cannot be read back.
Output Mode - Any GPIO pin can be configured for output mode. The GPIO output drivers are enabled by setting
the corresponding bits in the PORT_DIR, PORT_DIR_SET, or
PORT_DIR_CLR
registers. By using the
PORT_DIR_SET
and
PORT_DIR_CLR
registers, the direction of the signal flow of individual GPIO pins can be
altered by separate software threads without mutually impacting other GPIOs on the same port. Both registers re-
turn the same value when read. Because the state of the GPIO output can already be controlled before the output
driver is enabled, it is recommended to first set or clear the bit (using the PORT_DATA, PORT_DATA_SET, or
PORT_DATA_CLR
registers) to avoid any volatile levels on the output.
Open-Drain Mode - Every GPIO can also be used in open-drain mode. To accomplish this, first, clear the respective
bit in the
PORT_DATA
or
PORT_DATA_CLR
register. Then, set the one bit in the
PORT_INEN
register. Reads
from the
register then return the status from the pin and do not return the state of the internal flip-
PORT_DATA
flop. By toggling the output driver through the
PORT_DIR_SET
and
PORT_DIR_CLR
register pair, the output
signal can be pulled low or three-stated as required. Note that the polarity of the driven signal can be inverted when
the internal flip-flop is set instead. When a GPIO port is used in open-drain mode, take care to not exceed the V
IH
operating condition associated with the respective pin.
14–28
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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