Analog Devices ADSP-SC58 Series Hardware Reference Manual page 825

ADSP-SC58x UART Register Descriptions
Interrupt Mask Set Register
The indicates interrupt request mask status (unmasked if set, masked if cleared) of UART status inter-
UART_IMSK
rupts. This register is not a data register. Instead it is controlled by the
register pair. Writing ones to
disables (masks) them. Reads from either register return the enabled bits. For more informa-
UART_IMSK_CLR
tion, see the UART_IMSK
ETXS (R/W1S)
Enable TX to Status Interrupt Mask
Set
ERXS (R/W1S)
Enable RX to Status Interrupt Mask
Set
EAWI (R/W1S)
Enable Address Word Interrupt Mask
Set
ERFCI (R/W1S)
Enable Receive FIFO Count Interrupt
Mask Set
ETFI (R/W1S)
Enable Transmission Finished Interrupt
Mask Set
Figure 17-15: UART_IMSK_SET Register Diagram
Table 17-14: UART_IMSK_SET Register Fields
Bit No.
(Access)
9 ETXS
(R/W1S)
8 ERXS
(R/W1S)
7 EAWI
(R/W1S)
17–38
UART_IMSK_SET
register description.
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Enable TX to Status Interrupt Mask Set.
Enable RX to Status Interrupt Mask Set.
Enable Address Word Interrupt Mask Set.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_IMSK_SET
enables (unmasks) interrupt requests, and writing ones to
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 No action
1 Unmask interrupt
0 No action
1 Unmask interrupt
0 No action
1 Unmask interrupt
and
ERBFI (R/W1S)
Enable Receive Buffer Full Interrupt
Mask Set
ETBEI (R/W1S)
Enable Transmit Buffer Empty Interrupt
Mask Set
ELSI (R/W1S)
Enable Line Status Interrupt Mask Set
EDSSI (R/W1S)
Enable Modem Status Interrupt Mask
Set
EDTPTI (R/W1S)
Enable DMA TX Peripheral Triggered
Interrupt Mask Set
UART_IMSK_CLR