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General-Purpose 2 Frame Sync Mode
This mode is useful for video applications that use two hardware synchronization signals, HSYNC and VSYNC.
The HSYNC signal can be connected to EPPI_FS1 and the VSYNC signal can be connected to EPPI_FS2.
Data Enable in General-Purpose 2 Frame Sync Transmit Mode
The EPPI_FS3 pin functions as a data enable (DEN) pin, when EPPI is configured in GP 2 FS transmit mode
and generating the frame sync internally. The bits EPPI_CTL.MUXSEL and EPPI_CTL.CLKGATEN are not en-
abled. The functionality of the DEN pin is described in the following two cases.
Case 1
Blanking generation is configured using the EPPI_CTL.BLANKGEN bit. EPPI data length
(EPPI_CTL.DLEN bit) is configured for 8, 10, or 16-bit transfers. The EPPI_FS3 pin asserts during the
active data regions, aligned with EPPI_CLK according to the clock polarity (EPPI_CTL.POLC bit) set-
tings. For this mode, the pin EPPI_FS3 is driven based on the EPPI_CTL.POLC setting. The pin
EPPI_FS3 is driven out on the same EPPI clock edge that drives out data. The frame sync polarity
(EPPI_CTL.POLS) setting does not apply here—EPPI_FS3 is always active high in this mode.
Case 2
Blanking generation (EPPI_CTL.BLANKGEN =0) is disabled. Or blanking generation is enabled, but the
EPPI data length (EPPI_CTL.DLEN bit) is configured for a transfer size other than 8, 10, or 16 bits. The
EPPI_FS3 pin asserts at the start of the active data region on each line, aligned with EPPI_CLK according
to the EPPI_CTL.POLC bit settings. For this mode, the pin EPPI_FS3 is driven based on the
EPPI_CTL.POLC setting. The EPPI_FS3 signal is driven out on the same EPPI clock edge that drives out
data.
The EPPI_CTL.POLS bit setting does not apply for case 2. The EPPI_FS3 signal is always active high in
this mode. Once asserted, EPPI_FS3 stays asserted for the number of clock cycles per line configured in the
register, then it deasserts. This behavior on each line continues for the total number of lines
EPPI_HCNT
programmed in the
frames.
In case 2, if transmission of valid data is held off due to delays programmed in the
registers, the assertion of EPPI_FS3 is also held off. The delay is on a per-line or per-frame
EPPI_VDLY
basis.
General-Purpose 3 Frame Sync Mode
This mode is useful for video applications that use three synchronization signals for hardware: HSYNC, VSYNC,
and FIELD. The HSYNC connects to the EPPI_FS1 pin, VSYNC connects to the EPPI_FS2 pin, and FIELD
connects to the EPPI_FS3 pin.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
EPPI_VCNT
register per frame. The behavior repeats at the start of subsequent video
General-Purpose EPPI Modes
EPPI_HDLY
or
18–21
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