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Frame Sync 2 Delay Value Register
The
EPPI_FS2_DLY
first rising edge of EPPI_CLK after EPPI enabled and the first active edge of the associated frame sync when the
internal frame sync is used.
Note that if the
EPPI_FS1_DLY
ates as though 0 value is 1, and the first frame sync transition occurs after the completion of one period value of the
respective counters.
FS2_DLY[15:0] (R/W)
Frame Sync 2 Delay Count
FS2_DLY[31:16] (R/W)
Frame Sync 2 Delay Count
Figure 18-22: EPPI_FS2_DLY Register Diagram
Table 18-56: EPPI_FS2_DLY Register Fields
Bit No.
(Access)
31:0
FS2_DLY
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register selects the delay count (based on the period of the EPPI_CLK clock) between the
or
EPPI_FS2_DLY
15
0
31
0
Bit Name
Frame Sync 2 Delay Count.
The EPPI_FS2_DLY.FS2_DLY bit field selects the delay count.
registers are programmed with the value 0, the EPPI oper-
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x EPPI Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
18–69
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