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ADSP-SC58x PORT Register Descriptions
Port x GPIO Data Register
The operation of the
PORT_DATA
both modes, a set bit in the
PORT_DATA
register corresponds to a signal low on a GPIO pin.
The PORT_DATA, PORT_DATA_SET, and
mode. To enable output mode (and output drivers), use the
Writes to the
PORT_DATA
specific pins without impacting other pins of the port, use the
ters.
When the GPIO pins are in input mode (input driver is enabled with the
PORT_DATA, PORT_DATA_SET, and
Note that when the input driver is not enabled, reads from the PORT_DATA, PORT_DATA_SET, and
registers return the value previously written to the registers.
PORT_DATA_CLR
PX15 (R/W)
Port x Bit 15 Data
PX14 (R/W)
Port x Bit 14 Data
PX13 (R/W)
Port x Bit 13 Data
PX12 (R/W)
Port x Bit 12 Data
PX11 (R/W)
Port x Bit 11 Data
PX10 (R/W)
Port x Bit 10 Data
PX9 (R/W)
Port x Bit 9 Data
PX8 (R/W)
Port x Bit 8 Data
Figure 14-7: PORT_DATA Register Diagram
14–14
register depends on whether the bit/pin is in output mode or input mode. In
PORT_DATA
register corresponds to a signal high on a GPIO pin. A cleared bit in the
PORT_DATA_CLR
register affect the state of all pins of the port that are in output mode. To set or clear
PORT_DATA_CLR
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
25
0
0
0
0
0
0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers control the state of GPIO pins in output
PORT_DIR_SET
PORT_DATA_SET
PORT_INEN
registers return the state of the respective GPIO pins.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
and
PORT_DIR_CLR
and
PORT_DATA_CLR
register), reads from the
1
0
0
0
PX0 (R/W)
Port x Bit 0 Data
PX1 (R/W)
Port x Bit 1 Data
PX2 (R/W)
Port x Bit 2 Data
PX3 (R/W)
Port x Bit 3 Data
PX4 (R/W)
Port x Bit 4 Data
PX5 (R/W)
Port x Bit 5 Data
PX6 (R/W)
Port x Bit 6 Data
PX7 (R/W)
Port x Bit 7 Data
16
0
0
registers.
regis-
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